Toshio Yoshida

TL;DR: The Sparc64 VIIIfx eight-core processor, developed for use in petascale computing systems, runs at speeds of up to 2 GHz and achieves a peak performance of 128 gigaflops while consuming as little as 58 watts of power.

TL;DR: A processor includes an exponent generating unit that generates an exponent part of a coefficient represented by a floating point number format based on a first part of received input data, the coefficient being obtained when an exponential function is decomposed into a series operation and the coefficient for the series operation as discussed by the authors.

TL;DR: In this article, a cache control device comprises a command control section 43 for receiving a cache deterioration report and generating a cache flush mode initiation signal which performs degeneration of the cache 44, a software interrupt section 52 for interrupting the supply of commands from software in response to the cache flush-mode initiation signal, a command generating section 53a for generating fetch requests in which cache data flushing occurs, an address generating section 54 for generating addresses for flushing the cache data, and a request counter 58 for specifying ways at which flushing of cache will be performed, whereby degener

TL;DR: The authors enhanced the microarchitecture and introduced an extended instruction set called High-Performance Computing Arithmetic Computational Extensions (HPC-ACE), used previously in the K computer, to realize extremely high-throughput performance of Sparc64 X.

TL;DR: In this article, a processor system is made up of a multithread control unit (11) for selectively making switching among said threads to be executed in an arithmetic unit (150), a loop predicting unit (161) for predicting a loop of an instruction string on the basis of a processing history of a branch instruction in the thread, and a loop detecting unit (162) for detecting the loop, detecting an instruction.