PURPOSE:To enable sharp increase of the volume of a clutch and to relieve a control force, by a method wherein a starting clutch is placed in superposition with a change clutch to improve the degree of freedom of a layout, and the rotation force of a second clutch is converted into a press force to a pressure plate. CONSTITUTION:Starting and change clutch 11 and 13 are coaxially disposed on a driven shaft 14, the clutch 13 is formed with a pressure plate 18 adapted to interconnect a clutch center 16 and a clutch outer 15 by pressing a friction disc 17, and the clutch 11 is formed with a clutch shoe 20 forced into pressure contact with a second clutch outer 19. When the number of revolutions of a prime motor is increased to higher than a set value, a centrifugal force exerted on the shoe 20 is increased. The shoe 20 is connected to the second clutch outer 19, the clutch outer 15 is connected to the second clutch outer 19, a loading plate 35 presses and moves the plate 18 in the direction of the clutch center 16 through the action of a cam ball 37 to force the friction plate 17 into a pressure contact state, and a power is transmitted from an output shaft 25 to the shaft 14.

Clutch device for vehicle

PURPOSE:To attain stable phase comparison even at a high speed signal by providing a latch means latching an n-bit parallel signal outputted from a full adder, and sending the latched signal to a D/A converter. CONSTITUTION:The comparator is provided with a 2nd latch means latching an n-bit parallel signal outputted from a synchronous binary up-counter with a 2nd control signal and sending the latched signal to a full adder and a 1st latch means connecting to an output stage of the full adder so as not to disregard a delay time difference between outputted n-bit parallel signals. The 1st latch means the n-bit parallel signals for a prescribed period in a prescribed timing in response to a 1st control signal outputted from a control signal generating means and outputs them to a D/A converter. Thus, the delay time difference between the n-bit parallel signals inputted to the D/A converter is absorbed.

Digital phase comparator

PURPOSE:To attain high resolution and high speed for a PLL circuit by extracting a latch data based on the leading/trailing edge of a reference clock and detecting phase difference information at the half clock of the reference clock. CONSTITUTION:Frequency division ratio control signals +G, -G are generated by detecting a phase difference between the output of a variable frequency divider 22 and an input signal DRF when the phase of a channel bit clock PLCK is led or retarded by a half of a master clock pm. A phase comparator 25 latches the output data of FFs 21-23 to FFs 26-29, the data is selected by the Q output of the FF 25 to detect it as a phase difference level. The input signal DRF is controlled so that the trailing of the PLCK is in the center. Since the signal of the frequency divider 22 and the input signal DRF are compared by a digital logic PLL circuit 4 in the shortest way and they are used after comparison in other blocks, high speed processing is attained.

Obata Hiroshi

Papers

Phase comparator of digital logic pll circuit