Phase comparator of digital logic pll circuit

TLDR: In this paper, the phase difference between the output of a variable frequency divider and an input signal DRF was used to attain high resolution and high speed for a PLL circuit by extracting a latch data based on the leading/trailing edge of a reference clock.

Abstract: PURPOSE:To attain high resolution and high speed for a PLL circuit by extracting a latch data based on the leading/trailing edge of a reference clock and detecting phase difference information at the half clock of the reference clock. CONSTITUTION:Frequency division ratio control signals +G, -G are generated by detecting a phase difference between the output of a variable frequency divider 22 and an input signal DRF when the phase of a channel bit clock PLCK is led or retarded by a half of a master clock pm. A phase comparator 25 latches the output data of FFs 21-23 to FFs 26-29, the data is selected by the Q output of the FF 25 to detect it as a phase difference level. The input signal DRF is controlled so that the trailing of the PLCK is in the center. Since the signal of the frequency divider 22 and the input signal DRF are compared by a digital logic PLL circuit 4 in the shortest way and they are used after comparison in other blocks, high speed processing is attained.