An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Switch Circuit and Method of Switching Radio Frequency Signals

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

Integrated RF front end with stacked transistor switch

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

Method and Apparatus Improving Gate Oxide Reliability by Controlling Accumulated Charge

A voltage-controlled oscillating circuit according to the present invention includes: a bias voltage generating circuit outputting a bias voltage according to a control voltage; and a ring oscillator circuit receiving supply of the bias voltage to operate. The bias voltage generating circuit generates the bias voltage using a feedback circuit formed by an operational amplifier receiving supply of a power source voltage to operate. Therefore, an influence of a high frequency component overlapped on the power source voltage, that is an influence of noise, is suppressed, thereby enabling stable generation of an output clock having a small variation in phase.

VCO circuit with wide output frequency range and PLL circuit with the VCO circuit

PROBLEM TO BE SOLVED: To provide a voltage control oscillating circuit which is provided with a wide oscillation frequency range, and also possible to suppress effect of power noises. SOLUTION: The voltage control oscillating circuit 10 of the present invention includes a drive voltage generation circuit 11 outputting a drive voltage Vos in response to a control voltage Vcn, and a ring oscillator circuit 20 operating by receiving supply of the drive voltage Vos. The drive voltage generation part 11 generates the drive voltage Vos using a feedback circuit formed by an operational amplifier 12 operating by receiving supply of a source voltage Vdd. Accordingly, an output clock CLKO having small phase jitters is stably generated by suppressing the effect of high frequency components superimposed on the source voltage Vdd, that is, noises.

Voltage control oscillating circuit and phase synchronization loop circuit provided with the same

Eine spannungsgesteuerte Oszillationsschaltung (10) gemas der vorliegenden Erfindung weist eine Treiber-Spannungserzeugungsschaltung (11), die eine Vorspannung (Vos) entsprechend einer Steuerungsspannung (Vcn) ausgibt, und eine Ringoszillatorschaltung (20) auf, die zum Betrieb eine Zufuhr der Vorspannung (Vos) empfangt. Die Treiber-Spannungserzeugungsschaltung (11) erzeugt die Vorspannung (Vos) unter Verwendung einer Ruckkopplungsschaltung, die aus einem Operationsverstarker (12) gebildet ist, der zum Betrieb die Zufuhr einer Energieversorgungsspannung (Vdd) empfangt. Daher wird ein Einfluss einer der Energieversorgungsspannung (Vdd) beaufschlagten Hochfrequenzanteils, das heist ein Einfluss einer Storung unterdruckt, wodurch eine stabile Erzeugung eines Ausgangstakts (CLKO) mit einer kleinen Phasenvariation ermoglicht wird.

Ota Yoshiyuki

Papers

VCO circuit with wide output frequency range and PLL circuit with the VCO circuit

Voltage control oscillating circuit and phase synchronization loop circuit provided with the same

VCO-Schaltung mit breitem Ausgangsfrequenzbereich und PLL-Schaltung mit der VCO-Schaltung