From the Publisher:
Although it originated as a method to study general dynamical systems, symbolic dynamics is useful in coding for data storage and transmission as well as in linear algebra. Requiring only a undergraduate knowledge of linear algebra, this first general textbook includes over 500 exercises.

An Introduction to Symbolic Dynamics and Coding

This paperd escribes a byte-oriented binary transmission code and its implementation. This code is particularly well suited for high-speed local area networks and similar data links, where the information format consists of packets, variable in length, from about a dozen up to several hundred 8-bit bytes. The proposed transmission code translates each source byte into a constrained 10-bit binary sequence which hase excellent performance parameters near the theoretical limits for 8B/10B codes. The maximum run length is 5 and the maximum digital sum variation is 6. A single error in the encoded bits can, at most, generate an error burst of length 5 in the decoded domain. A very simple implementation of the code has been accomplished by partitioning the coder into 5B/6B and 3B/4B subordinate coders.

A DC-balanced, partitioned-block, 8B/10B transmission code

We present a computing microsystem that uniquely leverages the bandwidth, density, and latency advantages of silicon photonic interconnect to enable highly compact supercomputer-scale systems. We describe and justify single-node and multinode systems interconnected with wavelength-routed optical links, quantify their benefits vis-a-vis electrically connected systems, analyze the constituent optical component and system requirements, and provide an overview of the critical technologies needed to fulfill this system vision. This vision calls for more than a hundredfold reduction in energy to communicate an optical bit of information. We explore the power dissipation of a photonic link, suggest a roadmap to lower the energy-per-bit of silicon photonic interconnects, and identify the challenges that will be faced by device and circuit designers towards this goal.

Computer Systems Based on Silicon Photonic Interconnects

The main bandwidth bottleneck in today's networks is in the access segment. To address that bottleneck, broadband fiber access technologies such as passive optical networks (PONs) are an indispensable solution. The industry has selected time-division multiplexing (TDM) for current PON deployments. To satisfy future bandwidth demands, however, next-generation PON systems are being investigated to provide even higher performance. In this paper, we first review current TDM-PONs; we designate them as generation C. Next, we review next-generation PON systems, which we categorize into C+1 and C+2 generations. We expect C+1 systems to provide economic near-term bandwidth upgrade by overlaying new services on current TDM-PONs. For the long term, C+2 systems will provide more dramatic system improvement using wavelength division multiplexing technologies. Some C+2 architectures require new infrastructures and/or equipment, whereas others employ a more evolutionary approach. We also review key enabling components and technologies for C+1 and C+2 generations and point out important topics for future research.

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Next-Generation Optical Access Networks

Codes for mass data storage systems

Methods are presented for the encoding of information into binary sequences in which the number of ZEROS occurring between each pair of successive ONES has both an upper and a lower bound. The techniques, based on the state structure of the constraints, permit the construction of short, efficient codes with favorable error-propagation-limiting properties.

Sequence-state methods for run-length-limited coding

An overview of a set of algorithms and data structures developed for compressed-memory machines is given. These include 1) very fast compression and decompression algorithms, for relatively small fixed-size lines, that are suitable for hardware implementation; 2) methods for storing variable-size compressed lines in main memory that minimize overheads due to directory size and storage fragmentation, but that are simple enough for implementation as part of a system memory controller; 3) a number of operating system modifications required to ensure that a compressed-memory machine never runs out of memory as the compression ratio changes dynamically. This research was done to explore the feasibility of computer architectures in which data are decompressed/compressed on cache misses/writebacks. The results led to and were implemented in IBM Memory Expansion Technology (MXT), which for typical systems yields a factor of 2 expansion in effective memory size with generally minimal effect on performance.

Algorithms and data structures for compressed-memory machines

This paper analyzes the performance of unbuffered Delta networks under a nonuniform (“hot-spot”) traffic pattern. Particular attention is paid to characterizing the overflow traffic of unsuccessfully transmitted packets. Analytic techniques are used to show that the overflow traffic from an unbuffered packet-switched Delta network is (fractionally) hotter than the offered load. Simulation techniques are used to extend this result to an unbuffered circuitswitched network with limited retrials. In addition, the distribution of the number of trials until a “cold” packet is successfully delivered is shown to have a decreasing hazard rate, which means that it becomes less and less likely with each successive trial that a packet is delivered successfully. The implications of these results for hierarchical networks, a class of networks for interconnecting a highly parallel, sharedmemory multiprocessor computer system, are discussed.

P. A. Franaszek

Papers

A DC-balanced, partitioned-block, 8B/10B transmission code

Sequence-state methods for run-length-limited coding

Algorithms and data structures for compressed-memory machines

Traffic studies of unbuffered Delta networks

Traffic Studies of Unbuffered Delta Networks.