Single-phase phase-locked loops (PLLs) are popular for the synchronization and control of single-phase grid-connected converters. They are also widely used for monitoring and diagnostic purposes in the power and energy areas. In recent years, a large number of single-phase PLLs with different structures and properties have been proposed in the literature. The main aim of this paper is to provide a review of these PLLs. To this end, the single-phase PLLs are first classified into two major categories: 1) power-based PLLs and 2) quadrature signal generation-based PLLs. The members of each category are then described and their pros and cons are discussed. This paper provides a deep insight into characteristics of different single-phase PLLs, and therefore, can be considered as a reference for researchers and engineers.

Single-Phase PLLs: A Review of Recent Advances

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数字信号处理 = Understanding digital signal processing

A power-line interference (PLI) removal method is proposed based on a previously published sliding discrete Fourier transform (SDFT) phase locking scheme (PLL), which extracts the nonstationary sinusoids from the electrocardiogram (ECG) signal. The proposed PLI canceler consists of SDFT PLL as a vital element, which can track the variation in center frequency of the PLI either 50 or 60 Hz. The PLI canceler involves the adaptive sampling frequency control in which the sampling frequency of SDFT filter is adaptively adjusted according to the center frequency variation of the interference. Since the in-phase and quadrature components of SDFT filter can provide instantaneous sinusoidal and cosinusoidal interference signals, the SDFT PLL is capable of tracking amplitude, phase, and frequency of the interference. Additional resonators of different bin indices are augmented with SDFT PLL to handle the dominant odd harmonics of PLI. Furthermore, the SDFT PLL is cascaded with another SDFT bin to eliminate the baseline wander present in the real-time ECG signal. The adaptive PLI canceler based on SDFT PLL offers the tracking capability of variant PLI, attenuation of 40 dB, less acquisition time of 0.2 s for a variant PLI of ±5 Hz, removal of dominant odd harmonics, and baseline wander with expense of sampling frequency. Experimental results prove the efficacy of the proposed method in nonstationary sinusoidal interference extraction. Experimental investigation on SDFT PLL using field programmable gate array demonstrates the feasibility of digital implementation of the proposed algorithm.

A Power-Line Interference Canceler Based on Sliding DFT Phase Locking Scheme for ECG Signals

To improve the disturbance rejection capability of phase-locked loops (PLLs), which are undoubtedly the most common synchronization tool in power and energy applications, using different filtering techniques have been suggested in the literature. Among these filtering strategies, the delayed signal cancellation (DSC) operator is highly popular probably because it can be easily tailored for different grid scenarios. The DSC operator(s) can be used either as an in-loop filter in the PLL structure or as a preprocessing filter before the PLL input. The latter case is often preferred mainly because it results in a faster dynamic response in the extraction of grid voltage parameters. In this paper, a combination of an adaptive DSC operator with multiple nonadaptive DSC operators is suggested as the PLL preprocessing stage. To compensate for the phase and amplitude errors caused by the nonadaptive operators, a compensator is designed and cascaded with them. The proposed filter requires a low computational burden for the implementation and ensures a fast dynamic response and high filtering capability for the PLL. The effectiveness of this technique is verified through experimental results.

Hybrid Adaptive/Nonadaptive Delayed Signal Cancellation-Based Phase-Locked Loop

Voltage sag and swell mitigation based on modulated carrier PWM

The frequency tracking performance of sliding discrete Fourier transform (SDFT)-based phase locking (PLL) scheme has been improved by supplementing a cosine look-up table (cLUT) loop. Since the SDFT algorithm is marginally stable, to avoid instability, a damping factor is introduced, which causes the steady-state error in the PLL behaviour. The addition of cLUT indirectly strengthens cosine component of SDFT output and eliminates the effect of damping factor. Consequently, the numerically controlled oscillator (NCO) yields accurate sampling frequency, and it could be utilised to generate unit sine and cosine reference signals, synchronous with the periodic input signal in power system applications. A mathematical model of the look-up table (LUT) assisted SDFT-based PLL has been developed to analyse the transient and steady-state behaviour and it substantiates the improvement in steady-state performance. The PLL exhibits second order under damped response resulting in faster acquisition and small reduction in pull-in range with zero steady-state error. The improvement in performance of the LUT-assisted SDFT PLL is investigated by simulation and experimental studies.

Phase locking scheme based on look-up-table-assisted sliding discrete fourier transform for low-frequency power and acoustic signals

An amplitude-modulated (AM) ultrasonic range finder using an online parameter estimation procedure is presented, which uses the sliding discrete Fourier transform (SDFT) algorithm for extracting the sinusoidal envelope from the received reference and ultrasonic signals. The received ultrasonic envelope contains an additive noise, which resembles another sine wave whose frequency is very close to that of the envelope. This gives rise to a low-frequency beat in the phase shift between the transmitted and received envelopes. Consequently, the estimated phase shows an equivalent phase jitter. The desired sinusoidal envelope signal cannot easily be separated from the noise signal, even by sharply tuned SDFT filters with phase-locked loops (PLLs). A parameter estimation procedure has been applied to remove these interharmonic signals with the help of comb filters. The PLL was strengthened by a cosine lookup table (LUT). By locating the envelope frequency far away from the interharmonic noise frequency, the convergence time could greatly be reduced. Simulation studies were conducted in the Matlab-Simulink-DSP builder environment, and ideas were implemented in a Cyclone-II field-programmable gate array (FPGA)-based range finder fabricated in the laboratory. The test results of the AM ultrasonic range finder are presented to show its performance for static and slowly moving objects.

SDFT-Based Ultrasonic Range Finder Using AM Continuous Wave and Online Parameter Estimation

A New Algorithm for Frequency Estimation in the Presence of Phase Noise

An ultrasonic range finder for mobile robots has been proposed which uses the sliding discrete Fourier transform (SDFT) for extracting the low frequency sinusoidal envelope of a modulated ultrasonic signal. The continuous wave method uses the phase shift between the envelopes of infrared and ultrasonic carriers modulated by identical low frequency sine waves, for range measurement. The infrared sensor receives the reference waveform almost instantaneously, while the envelope of the modulated ultrasonic signal undergoes a phase-shift proportional to the distance traversed. Any frequency-drift in the envelope, which may occur at the sending or the receiving end, is tracked and compensated by the integrated phase locked loop (PLL). The fundamental components corresponding to the envelopes of the received reference (IR) as well as the ultrasonic signals are extracted using the SDFT procedure, in real time. The phase shift is determined by the Park transform procedure. Extensive simulation studies have been made, in the MATLAB DSP Builder environment so as to implement the scheme into a single Cyclone-II FPGA chip.

Sliding DFT based ultrasonic ranger

This paper presents a single chip FPGA (Altera Cyclone II) controlled single phase inverter, programmed for the reduction of harmonics in the output voltage. Separate composite digital observers have been designed for extracting the fundamental and harmonic components of the voltage and the highly distorted current signals, particularly when the inverter supplies nonlinear loads. These observers have been embedded into the FPGA along with the controllers and I/O interfaces. The multiple observers yield very pure in-phase and quadrature voltage signals for use in the outer loop and similar signals for stabilizing the inner current loop. The Inverter could be modeled as a feed back control system with the fundamental component of the voltage as the desired output while the voltage harmonics take the role of noise creeping into the output. To obtain a very low total harmonic distortion in the voltage waveform, the well-known control strategy of using a very large feed back around the noise signal has been employed.

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P.A. Janakiraman

Papers

Phase locking scheme based on look-up-table-assisted sliding discrete fourier transform for low-frequency power and acoustic signals

SDFT-Based Ultrasonic Range Finder Using AM Continuous Wave and Online Parameter Estimation

A New Algorithm for Frequency Estimation in the Presence of Phase Noise

Sliding DFT based ultrasonic ranger

FPGA-based software implementation of series harmonic compensation for single phase inverters