We evaluate the impact of band-to-band tunneling (BTBT) on the characteristics of n-channel junctionless transistors (JLTs) A JLT that has a heavily doped channel, which is fully depleted in the off state, results in a significant band overlap between the channel and drain regions This overlap leads to a large BTBT of electrons from the channel to the drain in n-channel JLTs This BTBT leads to a nonnegligible increase in the off-state leakage current, which needs to be understood and alleviated In the case of n-channel JLTs, tunneling of electrons from the valence band of the channel to the conduction band of the drain leaves behind holes in the channel, which would raise the channel potential This triggers a parasitic bipolar junction transistor formed by the source, channel, and drain regions induced in a JLT in the off state Tunneling current is observed to be a strong function of the silicon body thickness and doping of a JLT We present guidelines to optimize the device for high on-to-off current ratio Finally, we compare the off-state leakage of bulk JLTs with that of silicon-on-insulator JLTs

Effect of Band-to-Band Tunneling on Junctionless Transistors

This paper reports an accurate method of measuring the anomalous leakage current in pass-gate MOSFET's unique to SOI devices. A high-speed measurement setup is used to provide experimental results, and to quantify the magnitude of leakage. Particularly, great care is taken to measure only the device leakage current and not the currents due to parasitic capacitances. Systematic influences of different factors such as temperature, bias, device history, and device structure on this leakage current are experimentally established,.

Transient pass-transistor leakage current in SOI MOSFET's

The silicon-on-thin-buried-oxide (SOTB) CMOSFET is one of the strong candidates for further scaling because of its smallest Vth variation and back-bias controllability. This study focuses on its reliability, i.e., the hot-carrier-injection (HCI) degradation for the n-channel MOS and the negative-bias temperature instability (NBTI) for p-channel MOS. A comparison of the SOTB CMOSFET with a conventional bulk CMOSFET showed that the SOTB structure, which has a low-dose channel without a halo implant, produces higher reliability. The impact of the wide-range back biasing in SOTB devices on reliability was determined, i.e., the back biasing changes the mechanism of the HCI degradation but does not affect the NBTI degradation.

Effects of Device Structure and Back Biasing on HCI and NBTI in Silicon-on-Thin-BOX (SOTB) CMOSFET

The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-/spl mu/m 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.

Approaches to extra low voltage DRAM operation by SOI-DRAM

In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack height, channel length, Gate and Body bias, and process parameters. Overall, we find that the Pmax can be improved by reducing stack imbalance as well as device leakage currents, namely, GIDL.

Power handling capability of an SOI RF switch

A quantitative model which relates the SOI (silicon-on-insulator) MOSFET breakdown voltage to key parameters such as channel length, SOI film thickness, and gate voltage is presented The SOI breakdown is caused by electron impact ionization current produced near the drain which is subsequently amplified by a parasitic lateral bipolar transition This model is based on analytic modeling, quasi-2-D simulation and experimental study of the maximum drain electric field in SOI, and a novel method for measuring the lateral BJT (bipolar junction transistor) current gain beta using GIDL (gate-induced drain leakage) current It can accurately model the breakdown voltage within 02 V for different channel lengths, gate voltages, and SOI film thicknesses >

P. Cheng

Papers

An accurate model of thin film SOI-MOSFET breakdown voltage