This paper presents quantitative techniques for the evaluation and comparison of pipelined digital systems. They are based on three measures of effectiveness: delay, average time/operation, and average cost/operation. Moreover, the techniques do not assume that there is an unbounded stream of operations to be performed, although this case is considered. The use of the analysis methods to compare different ways of pipelining a given algorithm is illustrated by an investigation of the pipelining of general four-neighbor cellular arrays. The methods can also be used to evaluate different algorithms for performing the same operation. This is illustrated by comparing three array algorithns for integer multiplication.

Effective Pipelining of Digital Systems

A tutorial summary of the basic considerations necessary for designing custom digital filter hardware is presented. Emphasis is placed on fundamental principles and not on promotion of a specific design approach. The paper begins with a review of quantization (finite-accuracy arithmetic) effects. This is followed by a discussion of the elements of digital filters and how they are constructed, a review of the important technologies available, and a discussion of how the elements are put together to make a system. As examples of recent vintage hardware, the final section discusses three multipliers suitable for use in digital filters.

https://ieeexplore.ieee.org/iel5/5/31191/01451727.pdf

Special-purpose hardware for digital filtering

A new algorithm for the multiplication of two n-bit numbers based on the synchronous computation of the partial sums of the two operands is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. Multiplier arrays for positive numbers and numbers in two's complement form based on the proposed technique are implemented. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and the interconnections of the cells are regular, well-suited for VLSI realization.

Multiplexer-based array multipliers

A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described. Initially, attention is focused on a circuit which is used to multiply streams of parallel unsigned data. We then give details of an algorithm which demonstrates that, with only a simple modification to the basic cell, the same array can cope with two's complement numbers. The resulting structure has a number of features which make it extremely attractive to LSI and VLSI. These include regularity and modularity.

Completely iterative, pipelined multiplier array suitable for VLSI

This paper describes the design and implementation of a high-speed low-power 16 by 16 two's complement parallel multiplier. The multiplier uses optimized radix-4 Booth encoders to generate the partial products, and an array of strategically placed (3,2), (5,3), and (7,4) counters to reduce the partial products to sum and carry vectors. The more significant bits of the product are computed from left to right using a modified Ercegovac-Lang converter. An implementation of the multiplier in 0.25- /spl mu/m static CMOS technology has an area of 0.126 mm/sup 2/, a measured delay of 4.39 ns, and a average power dissipation of 0.110 mW/MHz at 2.5 Volts and 100/spl deg/C.

Design and implementation of a 16 by 16 low-power two's complement multiplier

A logical network is proposed, and an example of an iterative array formed using it is discussed.

P. Csillag

Papers

Iterative logical network for parallel multiplication