P.H. Eaton

TL;DR: In this article, the distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique.

TL;DR: By utilizing a latch that is radiation hard at static clock frequencies the errors due to transients could be separated and the pulse structure of the propagating transients was studied using SPICE, and the implications of these pulsewidths will be discussed.

TL;DR: In this article, a mechanism for simultaneous charge collection on proximal circuit nodes interacting in a way as to truncate, or quench, a propagated voltage transient, effectively limiting the observed SET pulse widths at high LET.

TL;DR: In this article, single event transients (SETs) in digital circuits/processes are examined and shown to substantially mitigate traditional SEU static-latch hardening techniques below 0.25 /spl mu/m.

TL;DR: In this paper, the authors measured the single event-transient (SET) width as a function of cross-section over three CMOS bulk/epitaxial technology nodes (0.25, 0.18 and 0.13 mum) using an identically scaled programmable-delay temporal-latch technique.