This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.

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Modeling the effect of technology trends on the soft error rate of combinational logic

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

Characterization of soft errors caused by single event upsets in CMOS processes

Experimental evaluation

This paper focuses on the integration of the fault injection methodology within the design process of fault-tolerant systems. Due to its wide spectrum of application and hierarchical features, VHDL has been selected as the simulation language to support such an integration. Suitable techniques for injecting faults into VHDL models are identified and depicted. Then, the main features of the MEFISTO environment aimed at supporting these techniques are described. Finally, some preliminary results obtained with MEFISTO are presented and analyzed. >

Fault injection into VHDL models: the MEFISTO tool

The progression of implementation technologies into the sub-100 nanometer lithographies renew the importance of understanding and protecting against single-event upsets in digital systems. In this work, the effects of transient faults on high performance microprocessors is explored. To perform a thorough exploration, a highly detailed register transfer level model of a deeply pipelined, out-of-order microprocessor was created. Using fault injection, we determined that fewer than 15% of single bit corruptions in processor state result in software visible errors. These failures were analyzed to identify the most vulnerable portions of the processor, which were then protected using simple low-overhead techniques. This resulted in a 75% reduction in failures. Building upon the failure modes seen in the microarchitecture, fault injections into software were performed to investigate the level of masking that the software layer provides. Together, the baseline microarchitectural substrate and software mask more than 9 out of 10 transient faults from affecting correct program execution.

Characterizing the effects of transient faults on a high-performance processor pipeline

Fault injection is an effective method for studying the effects of faults in computer systems and for validating fault-handling mechanisms. The approach presented involves injecting transient faults into integrated circuits by using heavy-ion radiation from a Californium-252 source. The proliferation of safety-critical and fault-tolerant systems using VLSI technology makes such attempts to inject faults at internal locations in VLSI circuits increasingly important. >

Using heavy-ion radiation to validate fault-handling mechanisms

The question to what extent particle induced transients in combinational parts of a circuit propagate into memory elements is addressed in this paper An experimental method is presented in which the proportion of bit flips originating from heavy-ion hits in combinational logic is determined. It is proposed that a voltage pulse may only propagate through a limited number of transistor stages and still be latched. The proportion of all transients in combinational logic that were latched into registers was experimentally, estimated to be between 0.7/spl middot/10/sup -3/ and 2/spl middot/10/sup -3/ for a custom designed CMOS circuit. Very few multiple bit flips were observed during the experiments which indicates that the single bit flip model used in many high-level simulations is reasonable accurate. >

On latching probability of particle induced transients in combinational networks

Two fault injection techniques for experimental validation of fault handling mechanisms in computer systems are investigated and compared. One technique is based on irradiation of ICs with heavy-ion radiation from a 252Cf source. The other technique uses voltage sags injected in the power supply rails to ICs. Both techniques have been used for fault injection experiments with the MC6809E microprocessor. Most errors generated by the 252Cf method were seen first in the address bus, while the power supply disturbances most frequently affected the control signals. An error classification shows that both methods generate many control flow errors, while pure data errors are infrequent. Results from a simulation experiment show that that the low number data errors in the 252Cf experiments can be explained by the fact that many errors in data registers are overwritten owing to the normal program execution.

Two fault injection techniques for test of fault handling mechanisms

A two-step switch-level algorithm for fault simulation of transients in CMOS networks is presented. The first step models the fault propagation locally from the fault injection site to the subsequent CMOS blocks. It is shown that the pulse width of a transient is a vital parameter in the propagation process. A first-order RC network model for the prediction of the width of transients is used. The second step consists of a set of rules for the propagation of fully developed transients through basic CMOS blocks. The fact that transients may fade out during propagation is efficiently modeled by taking into account their pulse widths. The proposed algorithm shows good agreement with electrical-level simulations in predicting the effects of device-level transients. >

A switch-level algorithm for simulation of transients in combinational logic

Several realistic transistor fault models were applied to circuit-level simulation models of code checkers in order to investigate the run-time fault testing capability. Various implementations of checkers designed for the detection of stuck-at faults were examined. A coverage varying from 99% to 100% was obtained for transistor terminal short faults and from 40% to 85% for open faults. A minimum set of four fault models for simulation-based evaluation of the self-testing property is proposed.

P. Liden

Papers

Using heavy-ion radiation to validate fault-handling mechanisms

On latching probability of particle induced transients in combinational networks

Two fault injection techniques for test of fault handling mechanisms

A switch-level algorithm for simulation of transients in combinational logic

Transistor Fault Coverage for Self-Testing CMOS Checkers