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Author

P. Manikandan

Other affiliations: Karunya University
Bio: P. Manikandan is an academic researcher from VIT University. The author has contributed to research in topics: Low-dropout regulator & CMOS. The author has an hindex of 3, co-authored 13 publications receiving 26 citations. Previous affiliations of P. Manikandan include Karunya University.

Papers
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Journal ArticleDOI
P. Manikandan1, B. Bindu1
TL;DR: In this paper, an internally compensated dual-summed flipped voltage follower (FVF) low dropout (LDO) regulator is proposed, which uses a small miller capacitance (MC) and an active feed-forward compensation (AFFC) to internally stabilize the feedback loop.
Abstract: In this paper, an internally compensated dual-summed flipped voltage follower (FVF) low drop-out (LDO) regulator is proposed This LDO uses a small miller capacitance (MC) and an active feed-forward compensation (AFFC) to internally stabilize the feedback loop The active feed-forward compensator shifts an RHP zero of the miller capacitance to the load-dependent LHP zero A simple RC high-pass filter enhances the overshoot transient response of the LDO and stabilizes the feedback loop further with increased phase margin This LDO achieves settling time of 110 ns during overshoot and 32 ns during undershoot with edge time of 25 ns

19 citations

Journal ArticleDOI
P. Manikandan1, B. Bindu1
TL;DR: In this article, a transient enhanced flipped voltage follower (FVF) based capless low-dropout (LDO) regulator for wide range of load currents and capacitances is presented.

7 citations

Journal ArticleDOI
TL;DR: In this paper, an output capacitor-less flipped voltage follower (FVF) low dropout regulator with an active feed-forward compensator is presented, which consists of a miller capacitance.
Abstract: An output capacitor-less flipped voltage follower (FVF) low dropout regulator (LDO) with an active feed-forward compensator is presented. A simple compensator which consists of a miller capacitance...

6 citations

Proceedings ArticleDOI
15 Mar 2012
TL;DR: In this paper, a class-E power amplifier with modified driver for WLAN and Bluetooth applications is presented, where negative capacitance concept is implemented to reduce parasitic capacitances at the driver output node to shape the output voltage.
Abstract: A class-E power amplifier with modified driver for WLAN and Bluetooth applications is presented in this paper. It is shown that a parallel class-E power amplifier gives better output power at minimum input power levels compared to a conventional class-E power amplifier. A new modified driver stage is proposed which drives the power amplifier efficiently. Negative capacitance concept is implemented to reduce parasitic capacitances at the driver output node to shape the driver output voltage. The negative capacitance is implemented without external circuit and the driver circuit is fed with less than 5dBm input power at 2.4GHz operating frequency. The power amplifier gain is more than 20dBm with 40% PAE at 2.4GHz. The power amplifier and the modified driver circuitry were implemented in 0.18-µm UMC CMOS technology using Cadence tool.

6 citations

Journal ArticleDOI
P. Manikandan1, B. Bindu1
TL;DR: A capacitorless low-drop-out regulator with an NMOS pass transistor-based adaptive network to achieve high and constant power-supply rejection (PSR) for varying loads is presented.
Abstract: A capacitorless low-drop-out (LDO) regulator with an NMOS pass transistor-based adaptive network to achieve high and constant power-supply rejection (PSR) for varying loads is presented. The propos...

5 citations


Cited by
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Book ChapterDOI
01 Jan 2003
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

207 citations

Proceedings Article
01 Jan 2005
TL;DR: In this paper, the authors demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology, which enables a 90 mVp-p output droop for a 100mA load step with only a small on-chip decoupling capacitor of 0.6 nF.
Abstract: We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mVp-p output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm 2 and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm 2 .

24 citations

Journal ArticleDOI
TL;DR: In this article , the authors present the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid, focusing on specific parameter up-gradation to the overall improvement of the functionality.
Abstract: Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

14 citations

Journal ArticleDOI
TL;DR: A new structure of output capacitor-less AB-LDO is proposed, employing recycling-folded-cascode(RFC) amplifier, to optimize the different trade-offs and achieves faster dynamic response, better linear and load regulation without increasing power consumption.
Abstract: This paper starts with a comprehensive analysis of the trade-offs among various performance parameters in conventional adaptively biased low dropout regulator (AB-LDO) and then proposes a new structure of output capacitor-less AB-LDO, employing recycling-folded-cascode(RFC) amplifier, to optimize the different trade-offs. With this special structure, the proposed AB-LDO finally achieves faster dynamic response, better linear and load regulation without increasing power consumption. In addition, cascode compensation is employed to bring a wider load range while ensuring loop stability. Finally, the proposed AB-LDO is implemented in 0.18 μ m CMOS process and experimental results show that a low quiescent current (10–50.25 μ A), good load regulation of 0.48 mV/mA, undershoot of 92 mV and overshoot of 86 mV with high current efficiency of 99.95 % have been achieved.

13 citations

01 Jan 2016
TL;DR: The design of a 2.4GHz class E power amplifier which consists of cascade stage with negative capacitance, which can transmit 16dBm output power to a 50Ω load is introduced.
Abstract: The objective of this research was to design a 2.4 GHz class E Power Amplifier (PA), with 0.18um Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence software, for health care applications. The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier which consists of cascade stage with negative capacitance. This power amplifier can transmit 16dBm output power to a 50Ω load. The power gain could reach 96 dBm and the total power consumption was 2.061 W. The performance of the power amplifier meets the specification requirements of the desired.

10 citations