Silicon interposers are providing interesting alternatives to organic packages for the fabrication of complex system in package (SIP) modules in particular for RF application. Among the advantages of this technology are the capability to fabricate fine pitch redistribution layers and to embed inside the interposer some high quality passive elements very close to the active chips resulting in a highly integrated solution. To keep the technology at a reasonable cost these last add-on features need to be fabricated with no or minor additional process steps that the ones needed for the fabrication of the interposer itself. In this work we present the design and the fabrication of a high resistive silicon interposer conceived for hosting a functional RF SIP transceiver including a Front End Module (FEM), a Dual Band Dual Mode Power Amplifier working at 400 and 900 MHz and some embedded planar and 3D inductors. The interposer consists in symmetrical stack with one thick level of copper RDL on each side of the 200 µm thin HR silicon substrate and connected with through silicon via-last (TSV-last). The inductors are built with no additional metallization level. For the inductors development, a dedicated test vehicle was first designed to study different designs including planar spirals and 3D solenoids and torus. Simulation work was first carried out for dimensioning the structures to target inductance values in the range of 0.5 to 10 nH and high quality factor greater than 20. We present the process used for the fabrication, in particular the realization of the thick copper RDL layers on both sides of the interposer and the of the TSV-last module. Physical characterization are presented showing the integrity and the good control of the technology. DC and RF electrical measurements assess the performances achieved for the different inductor variants exhibiting low resistance, constant inductance up to 5 GHz and factor of quality higher than 30. The functional RF transceiver SIP module will be then presented. The architecture is an extremely compact multi chip module composed of four actives CMOS chips (VGA, VCO, modulator and the PA) stacked by flip chip with Cu/SnAg µbumps on the HR silicon interposer and surrounded by a hundred of passive SMD components. With this technology the footprint of the module is reduced by a factor of 2 in comparison with the same module made on a µPCB substrate. The signals and ground are fed through the thick copper RDL lines and the TSVs from LGA pads present on the backside of the interposer for assembly on a test board. Different design configurations are made on the same wafer that include some version using only SMD inductors and some using 2.5 and 3D inductors in order to compare the corresponding performances. Other test structures are also present like filters and individual inductors for DC and RF characterization. We will finally present the resulting performances obtained from this SIP integration.

Highly Compact RF Transceiver Module Using High Resistive Silicon Interposer with Embedded Inductors and Heterogeneous Dies Integration

In this paper, new parallel plate coupler based Doherty power amplifier design for 5G NR handset applications is proposed. Based on simplified output network, the proposed Doherty power amplifier is analyzed. The proposed Doherty power amplifier is demonstrated experimentally with GaAs-HBT. A PAE of 42.0% and a NR ACLR of −38.8 dBc at an average output power of 27.8 dBm are measured at 3.75 GHz under 5G NR 100 MHz, DFT-s-OFDM, QPSK operation, and the efficiency improvement from Class AB operation achieves 11%. Moreover, the proposed Doherty power amplifier maintains more than 35.0% efficiency with a NR ACLR of below −35.2 dBc from 3.35 GHz to 4.15 GHz, corresponding to 5G NR Band n77.

Parallel Plate Coupler Based Doherty Power Amplifier Design for 5G NR Handset Applications

A reconfigurable broadband Doherty PA module for LTE HPUE (High Power User Equipment) applications is presented, which is the first to be based on an SOI-CMOS PA without predistortion and supply modulation. The PA die (1.3×1.7mm2) is fabricated in a 130nm SOI-CMOS process and assembled, using flip-chip, on a 3.2×3.7mm2 laminate package. From 1.9GHz to 2.7GHz, the PA provides 28dBm of output power (P out ) under 3.4V supply voltage (Vdd), with a PAE higher than 35% and an E-UTRA ACLR lower than -35dBc when using a 10MHz-50RB QPSK LTE uplink signal, without predistortion. At 2.3GHz, the proposed PA achieves 43.5% of PAE and -39.6dBc of ACLR at 28dBm of P out . When operating at Vdd=5V (HPUE mode), the PA reaches a saturated power of 4W with a maximum PAE of 57% and delivers a P out of 31dBm with 42.6% of PAE and -35.7dBc of ACLR using a 20MHz-100RB QPSK LTE signal.

A Reconfigurable SOI CMOS Doherty Power Amplifier Module for Broadband LTE High-Power User Equipment Applications

Navigating through intersections is one of the main challenging tasks for an autonomous vehicle. However, for the majority of intersections regulated by traffic lights, the problem could be solved by a simple rule-based method in which the autonomous vehicle behavior is closely related to the traffic light states. In this work, we focus on the implementation of a system able to navigate through intersections where only traffic signs are provided. We propose a multi-agent system using a continuous, model-free Deep Reinforcement Learning algorithm used to train a neural network for predicting both the acceleration and the steering angle at each time step. We demonstrate that agents learn both the basic rules needed to handle intersections by understanding the priorities of other learners inside the environment, and to drive safely along their paths. Moreover, a comparison between our system and a rule-based method proves that our model achieves better results especially with dense traffic conditions. Finally, we test our system on real world scenarios using real recorded traffic data, proving that our module is able to generalize both to unseen environments and to different traffic conditions.

End-to-End Intersection Handling using Multi-Agent Deep Reinforcement Learning

This work presents a 2.4-GHz load-modulated balanced amplifier (LMBA) designed for a linear AM-PM characteristic. The balanced amplifier is designed in class-J to ensure high back-off efficiency, while the optimal load trajectory is found through experimental characterization of the amplifier in CW. When operated as an RF-input LMBA, the amplifier demonstrates 54 and 49% drain efficiency (DE) at peak output power and 6-dB back-off, respectively, with only 4 degrees of AM-PM variation across this power range.

Load Modulated Balanced Amplifier Designed for AM-PM Linearity

This paper presents a broadband high-efficiency linear Doherty power amplifier (DPA) for LTE/LTE-A handset applications. The proposed PA is implemented in a 130nm SOI technology and packaged using flip-chip on a laminate substrate. At 2.5GHz, the PA shows a PAE of 44%, a power gain of 27dB, and an E-UTRA ACLR of −35dBc at 28dBm output power using a 10MHz LTE uplink signal without DPD. Moreover, the PA reaches a maximum FOM (PAE+|ACLR|) of 80 and maintains a FOM greater than 70 over 31% of fractional bandwidth around 2.3GHz without using DPD. When using DPD, the ACLR is improved by 10dB leading to a maximum FOM of 90. To the best of our knowledge, these performances represent the best linearity-efficiency performances compared to recently published LTE PAs for handset applications.

A Broadband High-Efficiency SOI-CMOS PA Module for LTE/LTE-A Handset Applications

This paper presents the first high-power SOI-CMOS power amplifier (PA) embedded in a Fan-Out Wafer Level Package (FOWLP) and addressing 2.4 GHz Wi-Fi 6 applications. At 2.44 GHz, the PA delivers 35.1 dBm of saturated output power (P sat ) with 53% of peak PAE and 29.5 dB of power gain. Without DPD, the PA achieves state-of-the art measured performance with 26.5/24.5/21.9 dBm of linear output power (P out ) for an EVM (Error Vector Magnitude) of −30/−35/−43 dB with an operating current of 336/270/210 mA for MCS7/9/11 40MHz signals respectively. The PA shows robust operation under extreme load mismatch (8:1 VSWR) and temperature (-40 to 80°C) conditions.

A High-Power SOI-CMOS PA Module with Fan-Out Wafer-Level Packaging for 2.4 GHz Wi-Fi 6 Applications

5G are stimulating major research efforts on next-generation power amplifiers (PAs). This paper presents a comprehensive overview of recent linear watt-level PA developments for mobile applications operating below 6GHz. A survey on state-of-the-art PAs is presented focusing on recently published envelope tracking and Doherty architectures.

Linear Power Amplifiers for Sub-6GHz Mobile Applications : Progress and Trends

The need for RF Front-Ends Module (FEM) with reduced size and cost is driving research towards highly integrated Power Amplifiers (PA) with challenging linearity and efficiency requirements. To overcome efficiency challenges, the Doherty PA (DPA) architecture represents an attractive solution because of its high back-off efficiency and relatively simple structure. This paper presents a state-of-the art SOI CMOS DP A design implemented in a 0.13um SOI CMOS industrial process. At 2.5GHz, the 2-stage SOI CMOS DPA achieves a measured peak PAE of 57% at 32.7dBm output power under 3.4V voltage supply. At IdB compression point, output power and PAE are 32.4dBm and 56% respectively. With a 10MHz LTE uplink signal, a linear output power of 29.4dBm is measured with a PAE of 48.8% at an ACLR level of −33dBc without using DPD.

P. Reynier

Papers

A Broadband High-Efficiency SOI-CMOS PA Module for LTE/LTE-A Handset Applications

A Reconfigurable SOI CMOS Doherty Power Amplifier Module for Broadband LTE High-Power User Equipment Applications

A High-Power SOI-CMOS PA Module with Fan-Out Wafer-Level Packaging for 2.4 GHz Wi-Fi 6 Applications

Linear Power Amplifiers for Sub-6GHz Mobile Applications : Progress and Trends

A 2.5GHz LTE Doherty Power Amplifier in SOI-CMOS Technology