The performance and reliability of microdevices can be strongly influenced by the peak temperature rise and spatial temperature distribution during brief electrical overstress (EOS) phenomena, which can occur at sub-microsecond time scales. The present study investigates short-time-scale laser reflectance thermometry of micro devices by examining the impact of passivation overlayers on the thermoreflectance signal and by demonstrating a calibration method suitable for metallization. This manuscript also describes a scanning laser thermometry facility that captures temperature fields in microdevices with 10 ns temporal resolution and 1 μm spatial resolution. The facility combines scanning laser optics with electrical stressing capability to allow simultaneous interrogation of the thermal and electrical behavior of devices. Data show the transient temperature distribution along the drift region of silicon-on-insulator (SOI) power transistors and along metal interconnects subjected to brief electrical stresses. The theory and experimental capability developed in this study are useful for studying short-time-scale thermal phenomena in microdevices and verifying models employed for their simulation.

Short-time-scale thermal mapping of microdevices using a scanning thermoreflectance technique

The triggering of grounded gate nMOSFET (gg-nMOS) and field-oxide devices (FOXFETs), essential for optimized ESD protection design, is addressed by TLP-pulsed emission microscopy. Current nonuniformity and instability effects in snapback operation under DC and TLP conditions are demonstrated. The comprehensive correlation of emission and electrical behaviour allows an improved interpretation of device operation. Technological influences on the trigger uniformity are discussed.

Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing

This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device finger width (W) and significantly influenced by the substrate and gate-bias conditions as well. This nonuniform current distribution is identified as a root cause of the severe reduction in ESD failure threshold current for the devices with advanced silicided processes. Additionally, the concept of an intrinsic second breakdown triggering current (I/sub t2i/) is introduced, which is substrate-bias independent and represents the maximum achievable ESD failure strength for a given technology. With this improved understanding of ESD behavior involved in advanced devices, an efficient design window can be constructed for robust deep submicron ESD protection.

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Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors

This paper presents a detailed study of the nonuniform bipolar conduction phenomenon in single finger NMOS transistors and analyses its implications for deep submicron ESD design. It is shown that the uniformity of lateral bipolar triggering is severely degraded with device width (W) in advanced technologies with silicided diffusions and low resistance substrates, and that this effect can only be improved up to a maximum W by increasing the substrate bias. Additionally, the concept of intrinsic second breakdown strength is introduced, which is substrate bias independent and represents the maximum achievable breakdown current for a given technology.

Non-uniform bipolar conduction in single finger NMOS transistors and implications for deep submicron ESD design

Dynamics and "travelling" modes of localized moving current filaments in electrostatic discharge (ESD) protection devices during current stress pulses are investigated using backside interferometric thermal mapping methods. The spatio-temporal evolution of the filament along the device width is related to the time evolution of the voltage waveform and to the IV characteristics of the device.

Moving current filaments in ESD protection devices and their relation to electrical characteristics

The purpose of this work is to present a new phenomenon in the ElectroStatic Discharge (ESD) failure threshold of deep submicron CMOS technologies. Although the bipolar conduction mode (or snapback) used for the protection was considered as uniform, we present dynamic EMission MIcroscopy (EMMI) studies showing for the first time that the current does not instantly spread out over the complete width of the transistor. Furthermore, this phenomenon leads to a saturation of failure threshold for the widest transistors and plays a major part in the failure threshold of devices. Different parameters having an influence on the spreading of the current are analyzed and interesting conclusions for the design of ESD hard NMOS devices are drawn.

P. Salome

Papers

Study of a 3D phenomenon during ESD stresses in deep submicron CMOS technologies using photon emission tool