Embedded passives are gaining in importance due to the reduction in size of electronic products. Capacitors pose the biggest challenge for integration in packages due to the large capacitance required for decoupling high performance circuits. Surface mount discrete (SMD) capacitors become ineffective charge providers above 100 MHz due to the increased effect of loop inductance. This paper focuses on the importance of embedded capacitors above this frequency. Modeling, measurements, and model to hardware correlation of these capacitors are shown. Design and modeling of embedded capacitor arrays for decoupling processors in the midfrequency band (100 MHz-2 GHz) is also highlighted in this paper.

Design, Modeling, and Characterization of Embedded Capacitor Networks for Core Decoupling in the Package

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Design of High Speed Packages and Boards Using Embedded Decoupling Capacitors.

To improve the electrical characteristics of LSIs, we are developing technology for embedding chip capacitors into interposers for LSIs. In this paper, we applied an interposer with embedded capacitors to an image-processing LSI and compared its electrical characteristics with that of a conventional LSI. We confirmed improvements in the timing margin, signal integrity, and immunity characteristics of the LSI.

An evaluation of the immunity characteristics of an LSI with capacitors embedded in an interposer

Due to increasing demands on the power delivery networks within current and next-generation computer systems, power integrity has become a leading focus, in addition to signal integrity, in system design. We will present a technology deployed within substrates, interposers, or sockets to enhance core power delivery. Our technology is comprised of a novel integration of decoupling capacitance between the core power nets and ground. This decoupling replaces the numerous decoupling capacitors suboptimally placed on traditional printed circuit boards (PCBs). The net result it lowered power supply noise and increased core power stability, permitting greater semiconductor switching frequency while reducing overall system cost. Studying actual system applications, we compare this technology to a wide range of expensive and largely ineffective decoupling strategies that have been proposed and even deployed, and demonstrate its superiority in both cost and performance.

P.T. Codd

Papers

A novel decoupling capacitance platform for substrates, sockets, and interposers