This paper describes the fabrication, characterization, and modeling of complementary metal-oxide-semiconductor (CMOS)-compatible capacitive micromachined ultrasound transducers (CMUTs). The transducers are fabricated using the interconnect and dielectric layers from a standard CMOS fabrication process. Unlike previous efforts toward integrating CMUTs with CMOS electronics, this process adds no microelectromechanical systems-related steps to the CMOS process and requires no critical lithography steps after the CMOS process is complete. Efficient computational models of the transducers were produced through the combined use of finite-element analysis and lumped-element modeling. A method for improved computation of the electrostatic coupling and environmental loading is presented without the need for multiple finite-element computations. Through the use of laser Doppler velocimetry, transient impulse response and steady-state frequency sweep tests were performed. These measurements are compared to the results predicted by the models. The performance characteristics were compared experimentally through changes in the applied bias voltage, device diameter, and medium properties (air, vacuum, oil, and water). Sparse clusters of up to 33 elements were tested in transmit mode in a water tank, achieving a center frequency of 3.5 MHz, a fractional bandwidth of 32%-44%, and pressure amplitudes of 181-184 dB re 1 μParms at 15 mm from the transducer on axis.

Modeling and Characterization of CMOS-Fabricated Capacitive Micromachined Ultrasound Transducers

Internal stress relaxation based method for elastic stiffness characterization of very thin films

As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 × 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 μm hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced.

A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS

Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35 μm 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli.

https://iopscience.iop.org/article/10.1088/0960-1317/25/2/025014/pdf

Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

Multilayered structures are increasingly used in MEMS. Based on the resonant frequency of the doubly–clamped multilayered beam, the Young's modulus and residual stress for an individual layer have been measured by designing beam test structures for each layer with different widths. Taking into account the buckling or no buckling problem of the multilayered beam, this paper introduces a model for the resonant frequency of the beam. An approach to extract the Young's modulus and residual stress for the individual layer is developed. The validity of this approach has been studied using finite element modeling. As a multilayered example, test structures for a gold/polysilicon bilayer beam were fabricated. A scanning laser Doppler vibrometer system was used to measure the resonant frequency of the beam. The extracted parameters are that the average value of Young's modulus of polysilicon and gold are 133.7 GPa and 78.6 GPa with standard deviation being 4.2 GPa and 11.5 GPa, respectively; the average value of residual stress of polysilicon and gold are 13.9 MPa (compressive) and 19.7 MPa (tensile) with standard deviation being 0.47 MPa and 4.4 MPa, respectively.

https://iopscience.iop.org/article/10.1088/0960-1317/24/7/075014/pdf

A simple method for extracting material parameters of multilayered MEMS structures using resonance frequency measurements

This letter1 presents a method to measure the Young's moduli of individual thin-film layers in a commercial integrated circuit (IC) foundry process. The method is based on measuring the resonance frequency of an array of micromachined cantilevers and using the presented optimization analysis to determine the elastic modulus of each layer. Arrays of cantilever test structures were fabricated in a commercial CMOS IC process and were released using XeF2 as a postprocessing etch. A piezoelectric transducer placed under the test chip was used to excite the cantilevers to resonance, and the resonance frequency was measured using a laser Doppler vibrometer. It is reported that excellent agreement for values of Young's modulus is observed for cantilevers between 200 and 400 mum in length, with average standard deviation being 4.07 GPa.

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P.T. Vernier

Papers

Young's Modulus Measurements in Standard IC CMOS Processes Using MEMS Test Structures