In this paper, we examine the concept of channel splitting in Gate All Around Tunnel Field Effect Transistor (GAATFET) and its impact on the performance of the device. The TFET device proposed in this work is designed for a channel length of 20nm and the channel region is divided with equal lengths on the same side. The doping concentration has been kept more towards the drain side channel. Numerical simulation using CAD device simulation software has been performed for investigating device performance. Results have been compared with the uniform channel GAATFET. Simulation results show that there is a reduction in off current by 1 decade in the case of split channel GAATFET. Further, a larger difference is found in the electron current density (ECD) of the split channel GAATFET. The subthreshold swing is also found to decrease to a value of 33.14 mV/decade. The threshold voltage was found to be 0.092V.

Impact of Channel Splitting on Gate All Around Tunnel Field Effect Transistor (GAATFET)

Low noise amplifiers are typically employed as high or intermediate frequency preamplifiers for various radio receivers. This document shows the implementation of CMOS Low Noise Amplifier using 180 nm current conveyor. When boosting weak signals, the amplifiers noise output may significantly interfere with the signal. To receive and amplify the very low-power signal that the antenna presents to it within the targeted bandwidth, it serves as the front end of the receiver channel. This is referred to as the most challenging signal processing task in signal theory. LTSPICE simulation with 180nm CMOS technology, has been carried out to test the integrity of the design.

Design of CMOS Low Noise Amplifier Using 180NM Current Conveyor

A low noise, all CMOS voltage reference is proposed and designed for defence applications. The proposed design uses a decoupling capacitor and chopper-stabilization-based-noise-cancellation technique. The design is supported with an extensive process, voltage and temperature (PVT) analysis in a standard 65 nm CMOS technology. The simulation results exhibit 0.89 V of $\mathbf{v}_{ref}$ with 13.03 ppm/°C temperature sensitivity. The design also shows a spot noise of 3.43 nV at 10 KHz, root mean square (RMS) noise $(\mathbf{V}_{rms})$ of 1.07 $\mu \mathbf{V}/\sqrt{Hz}$ for 10 Hz to 100 KHz and power supply rejection ratio (PSRR) of 72.83 dB, reported at various worst case PVT corners. At a typical PVT corner, the results show the spot noise of 2.78 nV at 10 KHz, $\mathbf{V}_{rms}$ noise of 0.88 $\mu \mathbf{V}/\sqrt{Hz}$ for 10 Hz to 100 KHz and the PSRR of 80 dB. The paper also presents the mathematical closed-form noise equations for the proposed circuit. The equations show the mean percentage error (MPE) of 1%, 0.3% and 0.5% for the mean square output noise, the spot noise and the RMS noise respectively.

A Low Noise Bandgap Reference with 0.89 V Vref, 0.88 μVrms noise and 80 dB of PSRR

Low-Noise Amplifiers are key components in every communication receiving end. The LNAs primary purpose is to amplify the weak input signal, adding additional little noise. A SiGe Low-Noise amplifier at design frequency of 3.5GHz is presented. This paper includes the bias network design, Stability analysis, Matching Network Design and EM Co-simulation of the LNA. Gain of ≥15dB, Noise Figure of ≤1dB is achieved to make sure noise contribution of the amplifier is as low as possible. Keysight's Advance Design Software tool has been used for simulation.

LNA Design for LEO Space S-Band Applications

The research aims to design a narrow-band frequency drive amplifier (1.5GHz -1.6GHz), which is used to boost the transmitter amplifier's input signal or amplify the GPS, GlONASS signals at the L1 band.
The Power Amplifier printed circuit board (PCB) prototype was designed using InGaP HBT homogeneous technology transistor and GaAs Heterojunction Bipolar Transistor (HBT) transistor. Two models have been compared; one of the models gave 16dB gain, and the other gave 23dB when using an input power signal (-15dBm). The PCB consumes 2.4W of power and has a physical dimension of 11 x 4 cm.

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Design narrow-band frequency amplifier (1.5GHz -1.6GHz) based on InGaP Heterojunction Bipolar Transistor (HBT) and GaAs HBT

In a radio frequency (RF) transceiver, low noise amplifier (LNA) plays a critical role in determining the receiver performance. This paper elucidates the design of an LNA for optimizing its gain, noise figure and stability factor with different transistor configurations in the frequency range of 5-6 GHz. Design-optimization of LNA has been performed with standard transistor (BJT and MOSFET) files in circuit simulation software. For comparison we have considered the following configurations of LNA: (i) a single stage npn BJT LNA, (ii) npn BJT and NMOS cascode LNA, and (iii) npn BJT and CMOS cascode LNA. Simulation results show that compared to other configurations npn BJT-NMOS cascode LNA depicts the highest gain of 20.42 dB and the lowest noise figure of 0.25. On the other hand, npn BJT-CMOS cascode LNA demonstrates the highest stability factor of 1.07 followed by npn BJT LNA and npn BJT-NMOS cascode LNA configurations respectively. Further improvement in the LNA performance metrics is feasible by parametric optimization of transistor parameters and passive elements in the matching network.

Pallabi Sarkar

Papers

Performance Analysis of Radio Frequency (RF) Low Noise Amplifier (LNA) with various Transistor Configurations