
 This paper demonstrates the impact of temperature variation on vertically stacked junctionless nanosheet field effect transistor (JL-NSFET) concerning analog/RF performances using different gate lengths (Lg) along with high-k gate dielectrics. A comprehensive analysis of analog/RF performances like transconductance (gm), gate capacitance (Cgg), gate to drain capacitance (Cgd), output conductance (gds), intrinsic gain (Av), maximum oscillation frequency (fMAX), gain frequency product (GFP), and cutoff frequency (fT) is carried out for the temperature range 77-400 K. Note that with the decrease in temperature from 400 to 77 K, there is an improvement in AV, GFP, fT, and fMAX by ~7.43%, ~78.4%, ~78.38%, ~50.9%, respectively. It is also found AV gets degraded with the downscaling of Lg from 16 to 8 nm. However, the same resulted in the improvement of RF performance. From detailed analysis, it is further observed that the usage of high-k gate dielectrics (k=22) in JL-NSFET devices is not suitable due to the depreciation of analog/RF FOMs. Moreover, it is also noted that the improvement in analog/RF performance (ΔFoM = FoM(T=400) – FoM(T=100)) resulted from lowering the temperature can further be improved by downscaling of Lg and by using low-k gate dielectric.

Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node

Impact of Drain Underlap and High Bandgap Strip on Cylindrical Gate All Around Tunnel FET and its Influence on Analog/RF Performance

Tunnel field-effect transistors (TFETs) have garnered great interest as an option for the replacement of metal–oxide–semiconductor field-effect transistors owing to their extremely low off-current and fast switching suitable for low-power-consumption applications. However, conventional doped TFETs have the disadvantage of introducing undesirable random dopant fluctuation (RDF) events, which cause a large variance in the threshold voltage and ambipolar leakage current at negative gate voltages. In this study, a simple approach for charge plasma-based doping-less TFETs (DL-TFETs), including the Ge/Si bilayer frame, which affects the RDF and low on-current issues, was developed by the commercially available Silvaco Atlas device simulator. The use of the Ge/Si bilayer enhances the on-current and point subthreshold swing to 1.4 × 10−6 A and 16.6 mV dec−1, respectively. In addition, the dependencies of the Ge/Si junction boundary position and Ge content were examined systematically to attain a firm understanding of the electrical features in DL-TFETs.

Simple Ge/Si bilayer junction-based doping-less tunnel field-effect transistor

In this paper, we examine the concept of channel splitting in Gate All Around Tunnel Field Effect Transistor (GAATFET) and its impact on the performance of the device. The TFET device proposed in this work is designed for a channel length of 20nm and the channel region is divided with equal lengths on the same side. The doping concentration has been kept more towards the drain side channel. Numerical simulation using CAD device simulation software has been performed for investigating device performance. Results have been compared with the uniform channel GAATFET. Simulation results show that there is a reduction in off current by 1 decade in the case of split channel GAATFET. Further, a larger difference is found in the electron current density (ECD) of the split channel GAATFET. The subthreshold swing is also found to decrease to a value of 33.14 mV/decade. The threshold voltage was found to be 0.092V.

Impact of Channel Splitting on Gate All Around Tunnel Field Effect Transistor (GAATFET)

Analytical modeling of a dual-material graded-channel cylindrical gate-all-around FET to minimize the short-channel effects

In a radio frequency (RF) transceiver, low noise amplifier (LNA) plays a critical role in determining the receiver performance. This paper elucidates the design of an LNA for optimizing its gain, noise figure and stability factor with different transistor configurations in the frequency range of 5-6 GHz. Design-optimization of LNA has been performed with standard transistor (BJT and MOSFET) files in circuit simulation software. For comparison we have considered the following configurations of LNA: (i) a single stage npn BJT LNA, (ii) npn BJT and NMOS cascode LNA, and (iii) npn BJT and CMOS cascode LNA. Simulation results show that compared to other configurations npn BJT-NMOS cascode LNA depicts the highest gain of 20.42 dB and the lowest noise figure of 0.25. On the other hand, npn BJT-CMOS cascode LNA demonstrates the highest stability factor of 1.07 followed by npn BJT LNA and npn BJT-NMOS cascode LNA configurations respectively. Further improvement in the LNA performance metrics is feasible by parametric optimization of transistor parameters and passive elements in the matching network.

Performance Analysis of Radio Frequency (RF) Low Noise Amplifier (LNA) with various Transistor Configurations

The effect of retrograde doping with a high-density layer on the performance of a cylindrical (cyl.) gate-all-around (GAA) tunneling field-effect transistor (TFET) has been investigated. The proposed device design incorporates retrograde doping (RD) along with a heterospacer (HeTS) on a silicon-germanium substrate. The proposed device also includes a suppressed drain (SD) and steep density film (SDF) to achieve the optimal ON-current (ION) but suppressed OFF-current (IOFF) across the drain tunneling junctions. Since a high gate potential results in band bending in the source and drain regions due to the fringing fields, the heterospacer dielectric causes steep energy-band bending on the source side, leading to a high current drivability. Furthermore, to mitigate reliability issues, the trap charges are analyzed. Enhanced switching and radiofrequency (RF) characteristics are achieved when retrograde doping is incorporated with a steep density film. The device design and simulation are performed using Synopsys three-dimensional (3D) technology computer-aided design (TCAD) software. Direct-current (DC) and transient characteristics such as IOFF, ION, the gate–source capacitance (Cgs), the gate–drain capacitance (Cgd), the transconductance (gm), the electric field intensity, and the average subthreshold swing (SSavg) are analyzed for the three proposed structures. The simulation results reveal that that the SD GAA RD HeTS SDF TFET exhibits enhanced performance compared with other device structures, showing a high ION of 1.64 × 10–5 A/µm, a diminished IOFF of 3.48 × 10–18 A/µm, a gm of 57 µS/µm at Vgs = 0.6 V, and the steepest subthreshold slope (SS) of 29 mV/decade, but without degradation of the current drivability.

Sanjana Tiwari

Papers

Performance Analysis of Radio Frequency (RF) Low Noise Amplifier (LNA) with various Transistor Configurations

An investigation of a suppressed-drain cylindrical gate-all-around retrograde-doped heterospacer steep-density-film tunneling field-effect transistor

In-silico Investigation of Cyl. Gate all Around (GAA) Tunnel Field Effect Transistor (TFET) Biosensor

Impact of Drain Underlap and High Bandgap Strip on Cylindrical Gate All Around Tunnel FET and its Influence on Analog/RF Performance

On-chip Analysis of Etched Drain based Cyl. GAA TFET with Elevated Density Strip