Park Yong Eue

TL;DR: An improved data transmission circuit for complementary metal oxide semiconductor (CMOS) dynamic random access memory devices having a data input buffer for converting transistor-transistor logic (TTL) input data signals to CMOS logic level true and complement data signals is described in this paper.

TL;DR: In this paper, a data transfer circuit for dynamic CMOS direct access memory devices, with a data input buffer for conversion of TTL input data to true and complementary data signals, with two transfer gate circuits, two inverters, which are connected between the appropriate transfer gate circuit and I/O input/output data bus lines, is presented, where each inverter can be driven by control of a block select clock signal.

TL;DR: In this paper, the authors describe a circuit de transmission de donnees for a memoire vive dynamique, which comprend un amplificateur-separateur d'entree de donnes 10, a paire de portes de transmission 100, 200, and an element inverseur connectes entre les ports de transmission respectives and des lignes bus d'E/S directe and complementaire.