A high-speed SerDes must meet multiple challenges including high-speed operation, intensive equalization technique, low power consumption, small area and robustness. In order to meet new standards, such a OIF CEI-25G-LR, CEI-28G-MR/SR/VSR, IEEE802.3bj and 32G-FC, data-rates are increased to 25 to 28Gb/s, which is more than 75% higher than the previous generation of SerDes. For SerDes applications with several hundreds of lanes integrated in single chip, power consumption is very important factor while maintaining high performance. There are several previous works at 28Gb/s or higher data-rate [1-2]. They use an unrolled DFE to meet the critical timing margin, but the unrolled DFE structure increases the number of DFE slicers, increasing the overall power and die area. In order to tackle these challenges, we introduce several circuits and architectural techniques. The analog front-end (AFE) uses a single-stage architecture and a compact on-chip passive inductor in the transimpedance amplifier (TIA), providing 15dB boost. The boost is adaptive and its adaptation loop is decoupled from the decision-feedback equalizer (DFE) adaptation loop by the use of a group-delay adaptation (GDA) algorithm. DFE has a half-rate 1-tap unrolled structure with 2 total error latches for power and area reduction. A two-stage sense-amplifier-based slicer achieves a sensitivity of 15mV and DFE timing closure. We also develop a high-speed clock buffer that uses a new active-inductor circuit. This active-inductor circuit has the capability to control output-common-mode voltage to optimize circuit operating points.

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10 -9 . The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm $^{2}$ per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s.

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

Breakthroughs in silicon photonics are changing the economics of network hardware and are enabling new directions in computer networking, compelling us to reexamine our previous assumptions regarding computer and network architectures. One such area that bears further study is the choice of network topology in a world where the distance between nodes is largely irrelevant, and where there is no inherent economic advantage to spatial locality. Network architects should be able to select topologies based on their merits and not merely from tradition. Combined with relaxed system-level packaging constraints, silicon photonics will likely lead to future datacenter architectures that look very different from today’s solutions. We present the design and implementation of Topanga, a packet switch optoASIC with the requisite technologies to free datacenter topologies from constraints induced by limited electrical reach. By means of our platform for integrating silicon photonics inside the package, Topanga provides optical I/O with lower energy per bit at lower cost per port than existing solutions.

Reimagining datacenter topologies with integrated silicon photonics

Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

Low power high speed receiver with reduced decision feedback equalizer samplers

This paper presents a fully-integrated chipset for 4×25 Gb/s transceiver gearbox along with laser driver and photo detector front-ends. The transceiver provides 10:4 multiplexing and 4:10 demultiplexing conversion, with built-in clock generation, equalization, and amplification. The optical front-ends are realized as 4-element arrays, presenting remarkable performance with commercial vertical-cavity surface-emitting lasers and photodiodes. Feedforward equalizers and continuous-time linear equalizers are employed to compensate for loss and distortion in both electrical and optical domains. Fabricated in 65 nm CMOS technology, these chips can be lumped together as a compact module with performance exceeding typical 100 GbE standards.

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology

A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches [1]. This paper describes a generic CMOS 25-to-30Gb/s SerDes for use within CDR or gearbox applications, targeting the draft requirements of the OIF 28G-VSR standard [2] and suitable for both 100GBASE-LR4/OTL4.4 gearbox and retiming applications, including CFP and CFP2 [3].

A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications

Apparatus and methods modulate the slew rate of high-speed edges of a differential digital signal. High-speed digital signals carried over printed circuit boards, backplanes, cables, and the like can radiate electromagnetic waves. These electromagnetic waves can cause electromagnetic interference (EMI), and are tightly regulated by appropriate agencies, such as the FCC. Common mode radiation from differential signals can also cause EMI. By modulating the slew rates of the rising and falling edges of the differential signal, and by applying negative feedback, symbol-rate related spurs can be spread over a wider frequency range than conventional spread spectrum clocking (SSC) techniques, and thus should generally be capable of greater EMI reduction than conventional SSC techniques.

Reduction of electromagnetic interference for differential signals

The present application is directed to data communication. More specifically, embodiments of the present invention provide a SerDes system that includes multiple communication lanes that are aligned using a clock signal. Each of the communication lanes comprises a receiver, a buffer, and a transmitter. The receiver uses multiple sampling lanes for data sampling and clock recovery. Sampled data are stored at the buffer and transmitted by the transmitter. There are other embodiments as well.

Serdes with high-bandwith low-latency clock and data recovery

Embodiments of the present invention provide techniques for duty cycle correction of clock signals An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal A duty cycle sensor generates a first correction signal based on the output clock signal The first correction signal is at least partially opposite of the output clock signal A duty cycle corrector generates a second correction signal based on the first correction signal The duty cycle corrector includes two or more transistors for generating the second correction signal The second correction signal is applied to the output clock signal There are other embodiments as well

Compact high speed duty cycle corrector

The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

Parmanand Mishra

Papers

A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications

Reduction of electromagnetic interference for differential signals

Serdes with high-bandwith low-latency clock and data recovery

Compact high speed duty cycle corrector

Continuous time linear equalization for current-mode logic with transformer