Cryptosystem designers frequently assume that secrets will be manipulated in closed, reliable computing environments. Unfortunately, actual computers and microchips leak information about the operations they process. This paper examines specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. We also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.

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Differential Power Analysis

This paper examines how monitoring power consumption signals might breach smart-card security. Both simple power analysis and differential power analysis attacks are investigated. The theory behind these attacks is reviewed. Then, we concentrate on showing how power analysis theory can be applied to attack an actual smart card. We examine the noise characteristics of the power signals and develop an approach to model the signal-to-noise ratio (SNR). We show how this SNR can be significantly improved using a multiple-bit attack. Experimental results against a smart-card implementation of the Data Encryption Standard demonstrate the effectiveness of our multiple-bit attack. Potential countermeasures to these attacks are also discussed.

Examining smart-card security under the threat of power analysis attacks

An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

Semiconductor device and display device

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

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Principles of Asynchronous Circuit Design: A Systems Perspective

A radio frequency identification exciter ( 200 ) includes a plurality of antenna elements ( 122 a-i ) that are spaced to define active areas ( 130 a-e ). A matrix switch ( 202 ) flexibly connects the plurality of antenna elements to an exciter circuit ( 203 ). Independent switches ( 204 a-i ) are selectively switched such that an electric field is generated between at least two antenna elements whereby radio frequency identification tags ( 132 ) in the vicinity of the two antenna elements are capacitively powered to exchange data with the exciter. Antenna elements other than the at least two antenna elements may be selectively coupled to a signal from the exciter circuit that inhibits activation of radio frequency identification tags in the vicinity of those antenna elements. The matrix switch preferably comprises polymer-based circuits.

Method and apparatus for selectively activating radio frequency identification tags that are in close proximity

Power reception circuits employable in portable data devices (e.g., smart cards) to derive power and/or data from an input AC power signal (e.g., an ASK modulated carrier signal). In one embodiment, the power reception circuit comprises a power rectifier (120), a shunt rectifier (142) and a shunting element (132). The power rectifier (120) is adapted to rectify the input power signal, yielding a rectified output waveform. The shunt rectifier (142) is connected in parallel with the power rectifier (120). The shunting element (132) is connected to the shunt rectifier (142) and is operable to regulate an output voltage or current waveform produced at the output of the power rectifier (120). In another embodiment, the power reception circuit includes an analog circuit (610) for recovering data from a modulated carrier signal. A decoupling device (630) isolates the analog circuit (610) from impedance variations of a load. A shunt device (640) diverts undesired current from the load.

Power reception circuits for a device receiving an AC power signal

A portable data device (400) having a power controller (430), a clock generator (428) and a digital circuit (432). The power controller (430) has an output signal. The output signal is representative of available power. The clock generator (428) is coupled to the output signal of the power controller (430) for generating a variable clock rate corresponding to the output signal. The digital circuit (432) is coupled to the clock generator (428), and the digital circuit (432) is controlled by the variable clock rate.

Portable data device efficiently utilizing its available power and method thereof

A 14-bit, 100-MS/s CMOS digital-to-analog converter (DAC) designed for spectral performance corresponding more closely to the 14-bit specification than current implementations is presented. This DAC utilizes a nonlinearity-reducing output stage to achieve low output harmonic distortion. The output stage implements a return-to-zero (RZ) action, which tracks the DAC once it has settled and then returns to zero. This RZ circuit is designed so that the resulting RZ waveform exhibits high dynamic linearity. It also avoids the use of a hold capacitor and output buffer as in conventional track/hold circuits. At 60 MS/s, DAC spurious-free dynamic range is 80 dB for 5.1-MHz input signals and is down only to 75 dB for 25.5-MHz input signals. The chip is implemented in a 0.8-/spl mu/m CMOS process, occupies 3.69/spl times/3.91 mm/sup 2/ of die area, and consumes 750 mW at 5-V power supply and 100-MS/s clock speed.

A 14 b 100 Msample/s CMOS DAC designed for spectral performance

A secure contactless smartcard is presented. No batteries are required as device power is extracted from the RF field. With the exception of an inductive loop antenna, no external components are required. The transceiver adheres to the ISO 14443 type B specification. This system-on-a-chip integrates the RF circuitry with a large digital circuit without benefit of external bypass capacitors. An isolation circuit is introduced that prevents coupling of digital noise into the receiver. A measured bit error rate of 3E-10 is achieved. Security is also improved as the isolation circuit increases the required time for differential power analysis (DPA) attack by a factor of 2/sup 22/. Three-pass mutual authentication is presented and an algorithm for data restoration in the event of a tear is shown. This device was fabricated in a 0.6-/spl mu/m double-poly, triple-metal CMOS process. The chip is 2.8 mm/spl times/2.9 mm and it requires 500 uA or approximately 2.5 mW of power.

Patrick L. Rakers

Papers

Method and apparatus for selectively activating radio frequency identification tags that are in close proximity

Power reception circuits for a device receiving an AC power signal

Portable data device efficiently utilizing its available power and method thereof

A 14 b 100 Msample/s CMOS DAC designed for spectral performance

Secure contactless smartcard ASIC with DPA protection