A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

Method and apparatus for providing DMA transfers between devices coupled to different host bus bridges

A computer system having a processor, a microcontroller, a flash ROM is provided with an address remapper for handling warm-boot events, and an arbiter for selectively assigning the ownership of the flash ROM to either the microprocessor or the microcontroller. The arbiter assigns the flash ROM initially to the microcontroller when power is initially provided to the system. After the flash ROM boots up and checks the integrity of the flash ROM and updates the content of the flash ROM with valid firmware if necessary, the microcontroller releases the flash ROM to the microprocessor to enable the computer system to proceed with the normal boot-up process. In this process, various system self tests are performed. Next, the microprocessor copies or shadows one or more portions of the flash ROM BIOS into a main memory array. After the shadow operation, the processor sets a remap bit to indicate that the ROM BIOS content has been copied into the main memory array. The setting of the remap bit enables the remapper to deflect accesses to the flash ROM. The restarting of the clock signal to the microcontroller to switch the ownership of the flash ROM back to the microcontroller. In the event that the microprocessor needs to regain access to the flash ROM contents, the microprocessor writes to the mailbox register of the arbiter to request access to the flash ROM. The microprocessor waits for a confirmation from the arbiter that the microcontroller is entering an idled mode. Next, the microprocessor halts the clock of the microcontroller. These events cause the microcontroller to float or tristate the signal lines going from the microcontroller to the flash ROM such that the microprocessor can drive the signal lines without any conflict potentials. In this manner, the microprocessor can still access the shared flash ROM after it has booted up. Thus, the system cost is reduced, the system reliability is enhanced, while the system accessibility to the flash ROM after the boot-up period is still preserved.

Flash ROM sharing between processor and microcontroller during booting and handling warm-booting events

A method and system for enhanced bus arbitration in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a number of sub-buses. A maximum number of sub-buses is specified for each processor and the processors are prioritized. Each time a bus request is received from a processor, the number of requested sub-buses is granted, if that number is equal to or less than the specified maximum number of sub-buses for that processor. If the requested number of sub-buses is greater than the specified maximum number of sub-buses for that processor the requested number is granted if no other processor has issued a bus request.

Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access

A method and system for input/output control in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously in response to one or more transfer requests. In response to a transfer request having a data address associated therewith, a particular target device is identified. The data address is then written into an address queue. Thereafter, one or more of the multiple sub-buses are utilized to transfer data to or from a single processor in response to a transfer request from a single processor. In response to a transfer request from multiple processors, one or more of the multiple sub-buses may be utilized separately to simultaneously transfer data to or from multiple processors.

Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access

An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions. Maximum performance is thereby achieved from the circuit functions accessed most frequently, while still achieving high performance from those circuit functions accessed less frequently. The IC may be provided with a processor core with features that support In-Circuit Emulation (ICE).

Integrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access and control arbitration

An apparatus and method for arbitrating bus ownership of a first communication bus ("C1-bus") for a plurality of C1-bus masters and arbitrating bus ownership of a second communication bus ("C2-bus") for a plurality of C2-bus masters. The apparatus further performs a DMA transfer, without processor assistance, between a first component coupled to the C1-bus and a second component coupled to the C2-bus.

Paul Mc Allister

Papers

Apparatus and method for performing arbitration and data transfer over multiple buses