Patent
Apparatus and method for performing arbitration and data transfer over multiple buses
TLDR
In this article, an apparatus and method for arbitrating bus ownership of a first communication bus ("C1-bus") for a plurality of C1bus masters and arbitrating the ownership of C2-bus masters was presented.Abstract:
An apparatus and method for arbitrating bus ownership of a first communication bus ("C1-bus") for a plurality of C1-bus masters and arbitrating bus ownership of a second communication bus ("C2-bus") for a plurality of C2-bus masters. The apparatus further performs a DMA transfer, without processor assistance, between a first component coupled to the C1-bus and a second component coupled to the C2-bus.read more
Citations
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Method and apparatus for providing DMA transfers between devices coupled to different host bus bridges
TL;DR: In this article, a method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization.
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Flash ROM sharing between processor and microcontroller during booting and handling warm-booting events
TL;DR: In this article, the authors propose an address remapper for handling warm boot events, and an arbiter for selectively assigning the ownership of the flash ROM to either the microprocessor or the microcontroller.
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Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access
Cang Ngoc Tran,James Allan Kahle +1 more
TL;DR: In this paper, the authors propose a method and system for enhanced bus arbitration in a multiprocessor system having multi-processors coupled to a system memory via a common wide bus, where each processor outputs a request to bus arbitration logic for a number of sub-buses.
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Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access
Cang Ngoc Tran,James Allan Kahle +1 more
TL;DR: In this paper, the authors propose a method and system for input/output control in a multiprocessor system having multi-processors coupled to a system memory via a common wide bus.
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Integrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access and control arbitration
James A. Colgan,Robert J. Divivier,John R. Gunther,Ralph W. Haines,Daniel R. Herrington,Brian J. Marley,Mario Nemirovsky,Dan Craig O'neill,Jianhua Helen Pang,Alexander Perez,Stephen C. Pries,Michael J. Shay,Kent Bruce Waterson,David S. Weinman +13 more
TL;DR: In this paper, a distributed bus access and control arbitration is proposed for In-Circuit Emulation (ICE) in an integrated circuit (IC), which includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical.
References
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Patent
Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
TL;DR: In this article, an arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master, which is responsive to high priority bus activities such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity.
Patent
Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture
Harold L. McFarland,Allen P. Ho +1 more
TL;DR: In this paper, the authors proposed a dual-bus architecture that includes a high-speed system bus, called the NexBus, and a slower peripheral bus or AB, which is coupled by control logic, including an arbiter (50) and an alternate bus interface (ABI) (60).
Patent
System direct memory access (DMA) support logic for PCI based computer system
Nader Amini,Patrick Maurice Bland,Bechara Fouad Boury,Richard Gerard Hofmann,Lohman Terence Joseph +4 more
TL;DR: In this paper, a direct memory access (DMA) support mechanism is provided for use in a computer system which comprises a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU.
Patent
Direct memory access apparatus and methods for transferring data between buses having different performance characteristics
TL;DR: In this paper, direct memory access (DMA) is used to transfer data between a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus").
Patent
Programmable DMA controller
TL;DR: In this paper, a direct memory access (DMA) controller regulates access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the input/output devices, an interrupt register storing bus access request of the devices, a resolver for selecting one of the i/O device to have access to the buses, a pointer register storing addresses of locations in the memory for communication with the one IO device via the bus and a sequence register storing an address of a location in the memories containing a channel program instruction which is to