Micromachining technology was used to prepare chemical analysis systems on glass chips (1 centimeter by 2 centimeters or larger) that utilize electroosmotic pumping to drive fluid flow and electrophoretic separation to distinguish sample components. Capillaries 1 to 10 centimeters long etched in the glass (cross section, 10 micrometers by 30 micrometers) allow for capillary electrophoresis-based separations of amino acids with up to 75,000 theoretical plates in about 15 seconds, and separations of about 600 plates can be effected within 4 seconds. Sample treatment steps within a manifold of intersecting capillaries were demonstrated for a simple sample dilution process. Manipulation of the applied voltages controlled the directions of fluid flow within the manifold. The principles demonstrated in this study can be used to develop a miniaturized system for sample handling and separation with no moving parts.

Micromachining a miniaturized capillary electrophoresis-based chemical analysis system on a chip

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

All one needs to know about fog computing and related edge computing paradigms: A complete survey

To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

FlexRay is a communication protocol heavily promoted on the market by a large group of car manufacturers and automotive electronics suppliers. However, before it can be successfully used for safety-critical applications that require predictability, timing analysis techniques are necessary for providing bounds for the message communication times. In this paper, we propose techniques for determining the timing properties of messages transmitted in both the static and the dynamic segments of a FlexRay communication cycle. The analysis techniques for messages are integrated in the context of a holistic schedulability analysis that computes the worst-case response times of all the tasks and messages in the system. We have evaluated the proposed analysis techniques using extensive experiments. We also present and evaluate three optimisation algorithms that can be used to improve the schedulability of a system that uses FlexRay.

/pdf/timing-analysis-of-the-flexray-communication-protocol-2izc5onqpj.pdf

Timing analysis of the FlexRay communication protocol

In this paper, we concentrate on aspects related to the synthesis of distributed embedded systems consisting of programmable processors and application-specific hardware components. The approach is based on an abstract graph representation that captures, at process level, both dataflow and the flow of control. Our goal is to derive a worst case delay by which the system completes execution, such that this delay is as small as possible; to generate a logically and temporally deterministic schedule; and to optimize parameters of the communication protocol such that this delay is guaranteed. We have further investigated the impact of particular communication infrastructures and protocols on the overall performance and, specially, how the requirements of such an infrastructure have to be considered for process and communication scheduling. Not only do particularities of the underlying architecture have to be considered during scheduling but also the parameters of the communication protocol should be adapted to fit the particular embedded application. The optimization algorithm, which implies both process scheduling and optimization of the parameters related to the communication protocol, generates an efficient bus access scheme as well as the schedule tables for activation of processes and communications.

/pdf/scheduling-with-bus-access-optimization-for-distributed-3g0o3vvb5w.pdf

Scheduling with bus access optimization for distributed embedded systems

Timing Analysis for the FlexRay Communication Protocol

In this paper we present an approach to the design optimization of fault tolerant embedded systems for safety-critical applications. Processes are statically scheduled and communications are performed using the time-triggered protocol. We use process re-execution and replication for tolerating transient faults. Our design optimization approach decides the mapping of processes to processors and the assignment of fault-tolerant policies to processes such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several heuristics which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

/pdf/design-optimization-of-time-and-cost-constrained-fault-11vp2o974v.pdf

Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems

In this study the authors are interested in safety-critical real-time applications implemented on distributed architectures supporting the time-sensitive networking (TSN) standard. The on-going standardisation of TSN is an IEEE effort to bring deterministic real-time capabilities into the IEEE 802.1 Ethernet standard supporting safety-critical systems and guaranteed quality-of-service. TSN will support time-triggered (TT) communication based on schedule tables, audio-video-bridging (AVB) flows with bounded end-to-end latency as well as best-effort messages. The authors first present a survey of research related to the optimisation of distributed cyber-physical systems using real-time Ethernet for communication. Then, the authors formulate two novel optimisation problems related to the scheduling and routing of TT and AVB traffic in TSN. Thus, the authors consider that they know the topology of the network as well as the set of TT and AVB flows. The authors are interested to determine the routing of both TT and AVB flows as well as the scheduling of the TT flows such that all frames are schedulable and the AVB worst-case end-to-end delay is minimised. The authors have proposed an integer linear programming formulation for the scheduling problem and a greedy randomised adaptive search procedure-based heuristic for the routing problem. The proposed approaches have been evaluated using several test cases.

/pdf/design-optimisation-of-cyber-physical-distributed-systems-u4m5bumlmk.pdf

Paul Pop

Papers

Timing analysis of the FlexRay communication protocol

Scheduling with bus access optimization for distributed embedded systems

Timing Analysis for the FlexRay Communication Protocol

Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems

Design optimisation of cyber-physical distributed systems using IEEE time-sensitive networks