An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Methods of constructing a wire interconnect structure on a substrate are described. The methods broadly comprise the steps of depositing a spacer layer on a surface of the substrate, depositing a mask layer on the spacer layer, and removing a first portion of the mask layer overlying a desired area on the substrate surface to expose the spacer layer underlying the first portion of the mask layer. The methods further comprise the step of etching the structure such that a first portion of the spacer layer overlaying the desired area is removed and such that a portion of the desired area is exposed, and the step of depositing a first conductive material on the exposed portion of the desired area such that a conductive post is formed on the substrate surface and mounted to the desired area. Some of the disclosed methods comprise additional steps for forming an interconnect structure on the opposite surface of the substrate and providing an electrical interconnect means between the two interconnect structures. Additionally, some of the disclosed methods comprise steps for forming fillets around the conductive post at the substrate surface.

Wire interconnect structures for connecting an integrated circuit to a substrate

A probe card assembly includes a probe card, a space transformer having resilient contact structures (probe elements) mounted directly to (i.e., without the need for additional connecting wires or the like) and extending from terminals on a surface thereof, and an interposer disposed between the space transformer and the probe card. The space transformer and interposer are “stacked up” so that the orientation of the space transformer, hence the orientation of the tips of the probe elements, can be adjusted without changing the orientation of the probe card. Suitable mechanisms for adjusting the orientation of the space transformer, and for determining what adjustments to make, are disclosed. The interposer has resilient contact structures extending from both the top and bottom surfaces thereof, and ensures that electrical connections are maintained between the space transformer and the probe card throughout the space transformer's range of adjustment, by virtue of the interposer's inherent compliance. Multiple die sites on a semiconductor wafer are readily probed using the disclosed techniques, and the probe elements can be arranged to optimize probing of an entire wafer. Composite interconnection elements having a relatively soft core overcoated by a relatively hard shell, as the resilient contact structures are described.

Probe card assembly and kit, and methods of making same

A process for forming elongated solder terminals (38) to connect a plurality of pads (21) on a semiconductor device (20) to a corresponding plurality of pads (12) on a supporting substrate (10) by, forming a means (32, 42) to maintain a predetermined vertical spacing between the semiconductor (20) and the supporting substrate (10) outside area of the pads, forming and fixing solder extenders (16) to each of the solder wettable pads on the substrate or the device to be joined, positioning the semiconductor device provided with solder mounds (22) on the solder mountable pads (21) over the supporting substrate with the solder mounds in registry with the pads (12) on the substrate with the solder extenders (16) positioned therebetween, the means to maintain vertical spacing located between and in abutting relation to the device and substrate, and heating the resulting assembly to reflow the solder mounds and the solder extenders while maintaining a predetermined spacing thus forming a plurality of hour-glass shaped elongated connections (38).

Process for forming elongated solder connections between a semiconductor device and a supporting substrate

An improved solder interconnection for forming I/O connections between an integrated semiconductor device and a support substrate having a plurality of solder connections arranged in an area array joining a set of I/O's on a flat surface of the semiconductor device to a corresponding set of solder wettable pads on a substrate, the improvement being a band of dielectric organic material disposed between and bonded to the device and substrate embedding at least an outer row of solder connections leaving the center inner solder connections and the adjacent top and bottom surfaces free of dielectric material.

Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making

The interconnecting joints between a semiconductor chip and a substrate are not uniform, but differ in shape or material The difference results in different abilities to withstand shear stress and increases the device lifetime A volume differential causes a stress resistance differential in the interconnection joints

Flip chip module with non-uniform connector joints

A method for forming contoured electrodes of polycrystalline silicon by grading the concentration of dopant diffused into the silicon layers during the deposition process. Upon etching the silicon after deposition to form electrodes, e.g., the gate electrode of a field effect transistor, the electrode is desirably tapered. Conductive and insulator layers subsequently deposited atop the tapered electrode are less subject to cracking and lifting off than standard electrodes.

Method for forming silicon conductive layers utilizing differential etching rates

A method for the in-situ boron doping of polycrystalline silicon is disclosed wherein the boron-to-silicon ratio is increased beyond the limit of solubility of boron in silicon. Using appropriate flow rates of SiH4, B2H6, and H2, and deposition temperature, boron rich silicon is deposited upon a substrate. The boron is in solution in the silicon to the limit of its solubility and is present in excess amounts in boron-rich phases believed to be boron silicides. The deposited boron-rich polycrystalline silicon is subjected to a thermal oxidation step during which the dissolved boron is depleted into the growing oxide while the boron-rich phases decompose allowing the freed boron to go into solution in the silicon to replace the boron which is lost to the thermal oxide. By proper selection of parameter values, based upon experimentally determined silicon resistivity-to-B2H6 flow rate-to-thermal oxidation relationships, the boron-rich phases are substantially eliminated from the polycrystalline silicon at the same time that the thermal oxidation step is completed thereby yielding minimum resistivity doped silicon in the final structure.

Paul T Lin

Papers

Flip chip module with non-uniform connector joints

Method for forming silicon conductive layers utilizing differential etching rates

Boron silicide method for making thermally oxidized boron doped poly-crystalline silicon having minimum resistivity

Verfahren zum dotieren von silizium

A method of doping silicon