Showing papers by "Paul W. Coteus published in 1995"

Lead frame package for electronic devices

Abstract: An electronic device packaging structure is described which contains a lead frame on which the electronic device is disposed. The electronic device has contact locations at one edge thereof. The lead frame has leads which extend under the electronic device and inwardly from the opposite direction. Wires are wire bonded between electronic device contact locations and the beam leads which extend under the electronic device and the ends of the leads which extend inwardly from the opposite direction. Two electronic devices are stacked in at an offset with respect to each to expose contact locations on the surface of each electronic device at an edge of each electronic device to form a stepped surface exposing a plurality of electronic device contact locations. Preferably, the chips are identical and rotated 180° with respect to each other. Some of the leads of the lead frame for the double dense memory extend continuously under the stack to provide signal inputs through bit, address, control, power and ground inputs to the electronic devices. These inputs are common between the adjacent chips. Wires are bonded from contact locations on each chip to common leads. If a lead is common and cannot be mixed with another common lead, for example, a control line, it is located at the center of the lead frame. Other leads are provided which are not common between the two chips, for example chip select lines. Wires are bonded between the contact locations on each chip and at least one of the common leads of the lead frame.

Clock distribution network

Abstract: A clock distribution network for synchronously coupled electronic communication systems that includes a clock distribution device having a phase locked loop for synchronizing the external clock signals provided to each semiconductive device with each other. The clock distribution device distributes a low speed clock to a large number of clocked semiconductor devices where those devices then internally generate high speed clocks in phase with the low speed clock. The low speed clocks are phase shifted with respect to each other to reduce radiated energy. The ratio of internal to external clock speed is also communicated to each chip so that the chips can be programmed to operate with a variety of external clock speeds. The phase shifting of the external clock to different chips is provided so that the chips can still communicate synchronously at the high speed internal clock.

Removable heat sink assembly for a chip package

Abstract: The invention employs a post type fastening member that provides, at one end, an insertion friction connection to the circuit card and at the other end, extending through the heat sink, a compression spring means that urges the heat sink toward the circuit card. A plurality of the post type fasteners are positioned around the periphery of the chip package to retain the heat sink parallel to the circuit card and compressing the chip package. The packaging structure of the invention permits larger area heat sinks than the chip package area to be supported by the circuit card with the only relationship with the chip being that of a compression thermal transfer contact and radiation shield.