Showing papers by "Payam Heydari published in 2015"

A 64-channel ultra-low power bioelectric signal acquisition system for brain-computer interface

Abstract: A 64-channel bioelectric signal acquisition system incorporating a CMOS ultra-low power amplifier array and serializer integrated circuit (IC) is presented. Each amplifier within the array employs a complementary differential topology with cross-coupled-pair active load to achieve ultra-low power and low-noise operation for a nominal gain of 39 dB. The serializer utilizes zero-power complementary switch network which is controlled by an on-chip synchronous counter-based control circuitry. Fabricated in a 130 nm CMOS process with an area of 5.45 mm2 (excluding pads), the IC is designed to operate in the weak inversion region, resulting in an estimated total power consumption of 14 μW. Each amplifier consumes 216 nW from 0.4 V supply and occupies 0.044 mm2 of die area. The measured input-referred voltage noise across 190 Hz of amplifier's bandwidth is 2.19 μVRMS, corresponding to a power efficiency factor of 11.7. Experiments show that this system effectively amplifies human electroencephalographic and electromyographic signals.

A low-power BiCMOS 50 Gbps G m -boosted dual-feedback transimpedance amplifier

Abstract: A single-channel 50 Gbps transimpedance amplifier (TIA) in 130nm SiGe BiCMOS process is presented. The proposed TIA is comprised of a gm-boosted dual-feedback common-base, an RC-degenerated common-emitter and an inductively degenerated emitter-follower. Accounting for 100 fF photodiode's input capacitance, the TIA achieves a measured transimpedance gain of 41 dBII and a measured RMS input-referred current-noise spectral density of 35.4 pA/√Hz over a wide 3dB-bandwidth greater than 50 GHz. It achieves an open eye at 50 Gbps with an RMS jitter of 2.3 ps (including the jitter contribution of test fixture). The TIA chip occupies 1×0.575 mm2 (including pads) of die area and dissipates 24 mW from a 2 V supply voltage (i.e., less than 0.5 mW per 1 Gbps).

Bottom-feed on-chip waveguide slot antenna for THz applications

Abstract: A novel bottom-feed on-chip waveguide slot antenna is proposed for THz applications. The slot antenna is realized using an on-chip waveguide cavity whose top and bottom plates are realized using consists of metal-6 (M6) and metal-2 (M2) layers, respectively, and the sidewall is implemented using an array of vias from M2 to M6. Instead of the traditional feeding of microstrip/CPW on the sides, this antenna is fed from the bottom, which is more area-efficient and can avoid parasitic radiation from the feed line. The on-chip SIW cavity prevents radiation into the lossy substrate and thus improves the radiation of the slot antenna. The simulated gain is 3 dBi, and the radiation efficiency is around 33% at 450GHz. The total area of this antenna is only 330 × 290 µm2.

A broadband nonlinear lumped model for silicon IMPATT diodes

Abstract: A new circuit model based on time-domain characterization of Impact Ionization Avalanche Transit-Time (IMPATT) devices is proposed. The model introduces a new 3rd order low-pass filter to accurately model the delay response of carrier drift inside the drift region, thereby capturing the dispersion caused by carrier diffusion. Moreover, non-stationary effects inside avalanche region as well as the impact of avalanche length modulation on the displacement current are modeled through nonlinear avalanche capacitance.

Millimeter-wave integrated circuits for wireless transceivers in BiCMOS technologies

Abstract: This invited paper provides an overview of important attributes of a BiCMOS process in designing high-performance mm-wave integrated circuits, and contends, through several design examples, that it is perhaps one of the best process technologies for wireless applications that seek both high level of integration and high performance. In comparative study of BiCMOS performance compared to Silicon CMOS or III-V technologies, system-level considerations and circuit design issues will be illustrated. Several case studies including mm-wave integrated circuits designed and fabricated in BiCMOS processes will be introduced to provide experimental proof to these comparative studies.