Showing papers by "Peter A. Beerel published in 1996"

High-performance asynchronous pipeline circuits

Abstract: This paper presents design and simulation results of two high-performance asynchronous pipeline circuits. The first circuit is a two-phase micropipeline but uses pseudo-static Svensson-style double edge-triggered D-flip-flops (DETDFF) for data storage in place of traditional transmission gate latches or Sutherland's capture-pass latches. The second circuit is a four-phase micropipeline with burst-mode control circuits. We compare our DETDFF and four-phase implementations of a FIFO buffer with the current state-of-the-art micropipeline implementation using four-phase controllers designed by Day and Woods for the AMULET-2 processor. We implemented Day and Woods's design and both of our designs in the MOSIS 1.2 /spl mu/m CMOS process and simulated them with a 4.6 V power supply and at 100/spl deg/C. Our SPICE simulations show that our DETDFF and four-phase designs have 70% and 30% higher throughput respectively than Day and Woods's design. This higher throughput for the DETDFF design is due to latching the data on both edges of the latch control, removing the need of a reset phase and simplifying the control structures. Our four-phase design, on the other hand, has higher throughput because of the simplified control structures and the removal of the latch enable buffers from the critical path. The four-phase design, though not quite as fast as the DETDFF design, requires much smaller area for data storage.

Optimizing average-case delay in technology mapping of burst-mode circuits

Abstract: This paper presents technology mapping techniques that optimize for average case delay of asynchronous burst-mode control circuits. First, the specification of the circuit is analyzed using stochastic techniques to determine the relative frequency of occurrence of each state transition. Then, subject to timing and area constraints, the technology mapper minimizes the sum of the cycle times of the state transitions, weighted by their relative frequencies. Unlike other technology mappers, our mapper is based on the single step transition model for delay which finds the true critical paths, avoiding the false path problem.

Estimation of energy consumption in speed-independent control circuits

Abstract: We describe a technique to estimate the energy consumed by speed-independent asynchronous (clock-less) control circuits. Because speed-independent circuits are hazard-free under all possible combinations of gate delays, we prove that an accurate estimate of their energy consumption is independent of relative component gate delays and can be determined by simulating only a small number of input patterns proportional to the size of the circuit's Signal Transition Graph specification. Specifically, we calculate the average energy per external signal transition consumed by a circuit. This can be used to compare the energy consumption between two different circuit implementations of the same specification, to calculate average energy for a given high-level operation, and to provide average circuit power when combined with delay information.

A Low-Control-Overhead Asynchronous Differential Equation Solver

Abstract: This paper describes the design of a high-performance asynchronous differential equation solver, a common DSP application The high performance is achieved by two means First, efficient self-timed datapath elements were designed, including a self-timed carry-bypass adder with low-overhead domino completion-detection and a staggered-evaluation precharged multiplier using carry-save-addition Second, asynchronous control circuit overhead was minimized to 12% by using an efficient 3D control circuit design style and timing assumptions to effectively hide control circuit delay The design has been simulated in a 12?m two-metal HP SCMOS process and compared to comparable synchronous designs Its average-case performance (simulated at 25°C and 5V) is estimated to be 37% faster than the synchronous worst-case performance (simulated at 100°C and 45V)

High-performance two-phase micropipeline building blocks: double edge-triggered latches and burst-mode select and toggle circuits

Abstract: New high-performance building blocks for two-phase micropipelines are presented, and pseudo-static Svensson-style double edge-triggered D-flip-flops (DETDFF) for datapath storage are developed in place of traditional capture-pass or transmission gate latches. A DETDFF FIFO buffer implementation is compared with the current state-of-the-art micropipeline implementation using four-phase controllers designed by Day and Woods for the AMULET-2 processor and also with Sutherland's original two-phase micropipeline. All three designs were simulated the MOSIS 1.2 /spl mu/m CMOS process under worst-case process corner with a 4.6 V power supply and at 100/spl deg/C. The authors' SPICE simulations show that the DETDFF design has 70% and 150% higher throughput than Day and Woods' and Sutherland's. Respectively. This higher throughput is due to latching the data on both edges of the latch control, removing the need for a reset phase and simplifying the control structures, In addition, two commonly used micropipeline event-control structures, the select and toggle elements, are implemented using the extended-burst-mode 3D synthesis system. Detailed simulations demonstrate that our implementations are up to 50% faster than traditional implementations. This speed advantage can be primarily attributed to careful applications of generalised C-elements rather than discrete basic gates.