Showing papers by "Peter Puschner published in 2011"

Worst-Case Execution Time Analysis for Processors showing Timing Anomalies ⁄

Abstract: The analysis of the worst-case execution time (WCET) requires detailed knowledge of the program behavior. On modern processors the instruction timing heavily depends on the processor state. WCET analysis therefore has to the model processor behavior in detail. This analysis is challenging in case of so called timing anomalies, which violate the continuity properties proportionality and continuity of the timing behavior. In this paper we present a formal definition of timing anomalies and a formal analysis of their impact on WCET analysis. So far, timing anomalies have been described in the composition of instruction sequences. We call them series timing anomalies. We show that timing anomalies are also a problem when composing the overall state of sub-states of the hardware, which we call parallel timing anomalies. The results show that most types of timing anomalies are an impediment to an ecient timing analysis. Some of them can be handled eectively by the proposed composition methods. Finally, we present dierent methods to avoid the occurrence of timing anomalies. This report is not a final treatise on timing anomalies, but provides a concise problem characterization including some hints on how to deal with timing anomalies respectively how to avoid them.

Using a Local Prefetch Strategy to Obtain Temporal Time Predictability

Abstract: Today's embedded systems are considering cache as inherent part of their design. Unfortunately, cache memory behavior heavily depends on the past references which model a large execution history and makes WCET analysis impractical. This paper presents a novel prefetch memory mechanism that simplifies the prediction of cache hits/misses because the memory access times are independent of the execution history. We use local prefetching into on-chip memory together with a custom-designed prefetch controller instead of cache memories to provide for time-predictable memory accesses. To be competitive in code execution time, our approach relies on a special organization of main memory and on a modified compiler that generates code layouts to allow for parallel prefetching from different memory banks. The proposed solution is still in a conceptual phase. The paper discusses design decisions and parameters to be explored.