A scan chain architecture which has a controller (10), and a multiplexer (24) is used to route test data through functional units (12, 14, 16, 18, 20, and 22). The controller (10) receives as input a serial data stream from an STDI terminal and demultiplexes this data stream to one of the functional units (six functional units are illustrated in FIG. 1). Each of the functional units is considered as one scan chain and therefore FIG. 1 has six scan chains (one for each functional unit). In addition, a seventh scan chain couples all output flip-flops in each of the functional units together between an output of the MUX (24) and the STDO terminal/pin. Therefore, a serial scan of a data stream can be done through one functional unit, the multiplexer (24) and into the output flip-flops of each function unit to make testing easier to set-up. In addition, various new scan chain cells and low power methods are used herein.

Serial scan chain architecture for a data processing system and method of operation

An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Using the data paths of the processor core, operating logic generates pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme. In one embodiment, generating the pseudo-random test patterns includes multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product, adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration, and outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for the peripheral devices.

Arithmetic built-in self-test of multiple scan-based integrated circuits

A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

A JTAG module (12) includes a master component (20) and any number of slave components (22). The master component (20) includes a TAP controller (24) and related control circuits. Through a control bus (35), the TAP controller (24) on the master component (20) controls boundary-scan registers (18) on the slave components (22). The boundary-scan registers (18) in the slave components (22) form a boundary-scan chain that originates and terminates at the master component (20). TAP controller circuitry may be omitted from the slave components (22). The boundary-scan registers (18) on the master and slave components (20, 22) are partitioned into external sections (26, 34) and internal sections (28, 36). The external sections couple to conductive traces (46) which are accessible from outside the module (12). The internal sections couple to conductive traces (48) which are substantially inaccessible from outside the module (12).

Hierarchically managed boundary-scan testable module and method

Intermodule testing in a computer system including a plurality of modules interconnected via a system bus is performed by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct the modules of the computer system. Intermodule test data is maintained in memory on each of the modules and is accessible through operations of the serial test bus. Intermodule test data is retrieved by the serial test bus and used to set up the modules so that one module drives the system bus with test signals defined by test vectors included within the intermodule test data. The remaining modules are set up to receive the test signals. Tables are developed in accordance with the intermodule test data to define which test signals drive which system bus leads and also which receiving modules receive the test signals. The signals which are received by the modules set up to receive the test signals are sampled and compared to what signals should have been received to detect errors in intermodule communications. The selection of the module used to drive the system bus is rotated until all modules have driven the system bus.

Intermodule test across system bus utilizing serial test bus

A boundary scan test circuit for inclusion into ASIC and or VLSI circuits which does not require any additional pads/pins to support full boundary scan functionality. The invention uses the power and capability of existing address and data buses to transfer test data into the integrated circuit under boundary scan test, and uses the same buses to transfer test results out of the integrated circuit under test to be interpreted by the test processor of the system.

Method and apparatus for bus executed boundary scanning

BUS EXECUTED SCAN TESTING METHOD AND APPARATUS Abstract of the Disclosure For LSI/VLSI integrated circuits which inherently have an address decoder and a data bus, an scan testing method and apparatus is presented which does not require additional pin connections to be dedicated for scan test implementation. Counter to the Joint Test Action Group approach, the present invention uses additional registers, multiplexers, and decoders in conjunction with the existing buses to provide test access to otherwise embedded layers of logic circuitry, without the addition of a single pin connection to a integrated circuit chip package. Further, since this test method and apparatus uses the data bus and registers just as the rest of the chip, slow and complex d.c. level shifting equipment is not required.

Bus executed scan testing method and apparatus

Voltage levels of an external bus are sampled with results stored to adjust both an output driver and input receiver. The resulting logic signal levels for the input/output (I/O) interface are maintained within acceptable ranges of the standard I/O signal levels.

Peripheral component interfacing system with bus voltage/logic supply comparison means

In an electronic IC package, an I/O PAD circuit design which protects 3 Volt optimized I/O functional circuits from damage due to the application of external 5 Volt signals to the I/O PAD both while the functional circuit design is powered on and powered off. When the I/O circuits associated with the I/O PAD are powered on, the present invention protects the I/O circuits by applying well known designs. However, when the I/O circuits associated with the I/O PAD are powered off, the present invention draws power from the external 5 Volt signal to activate additional transistors to protect the powered off I/O circuits.

5-volt tolerant bi-directional i/o pad for 3-volt-optimized integrated circuits

A monitor device connected between a pin for connection to the more positive lead of the voltage supply or the less positive voltage of the power supply and the more positive voltage supply conductors or the less positive voltage supply conductors on the integrated circuit substrate. The monitor circuit has a threshold circuit so insignificant perturbations will not trigger the monitor. The monitor circuit also has a reference voltage input such that the same circuit may be used for the more positive side of the power supply, as well as, the less positive side with straightforward modifications. When the monitor circuit detects a significant fault, i.e. one that could falsely switch part of the integrated circuit, it sets a flip-flop to record such an occurrence. The monitor flip-flop cannot be reset by the usual reset signals, in order to prevent it from being cleared by normal diagnostics and error recovery operations.

Philip W. Bullinger

Papers

Method and apparatus for bus executed boundary scanning

Bus executed scan testing method and apparatus

Peripheral component interfacing system with bus voltage/logic supply comparison means

5-volt tolerant bi-directional i/o pad for 3-volt-optimized integrated circuits

Supply connection integrity monitor