Patent
Method and apparatus for bus executed boundary scanning
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TLDR
A boundary scan test circuit for inclusion into ASIC and or VLSI circuits which does not require any additional pads/pins to support full boundary scan functionality is presented in this paper. But it does not use the same buses to transfer test results out of the integrated circuit under test to be interpreted by the test processor.Abstract:
A boundary scan test circuit for inclusion into ASIC and or VLSI circuits which does not require any additional pads/pins to support full boundary scan functionality. The invention uses the power and capability of existing address and data buses to transfer test data into the integrated circuit under boundary scan test, and uses the same buses to transfer test results out of the integrated circuit under test to be interpreted by the test processor of the system.read more
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References
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Patent
Hierarchical scan selection
TL;DR: In this paper, a hierarchical scan network consisting of a primary scan ring from which a multiplicity of scan sub-rings may be accessed is presented. But the scan path can be used to observe and control logic elements in the design via serial scan operations.
Patent
Partitioned scan-testing system
Jeffrey D. Bellay,Theo J. Powell +1 more
TL;DR: In this paper, a test partitionable logic circuit comprises a plurality of functional modules (26a)-(26n) interfaced with the exterior of the logic circuit with a data bus (20), address bus (16), and a control bus (12), each of the modules is addressable through an address decode/select circuit to operationally isolate the select modules and define a test boundary.
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TL;DR: A testable logic circuit includes parallel registers (72)-(80) for interfacing with a common internal bus (70), individually addressable by an address decoder (104) for storage of test vectors therein this paper.
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Flexible VLSI on-chip maintenance and test system with unit I/O cell design
Judy Lynn Teske,Daniel James Baxter,Don Adorian Daane,Buraian Deeru Boochiyaazu,David Howard Allen,Michael Francis Maas +5 more
TL;DR: In this article, a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins is described.
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