A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also supports the pre-existing architecture. Extension of the data word size from m bits to N bits entails widening the machine registers and data paths from m bits to N bits and sign-extending entities of m or fewer bits to N bits when they are loaded into registers. Some of the m-bit instructions, when operating on N-bit sign-extended versions of m-bit entities, produce an N-bit result that may not correspond to the correct m-bit result, sign-extended to N bits. For these instructions compatibility requires that the instructions be further defined to guarantee a sign-extended result. This means that separate N-bit instructions corresponding to these m-bit instructions are needed. The support for up to an N-bit virtual address space is provided in part by widening the virtual address data paths. The extended architecture supports the m-bit architecture's addressing with minimal additional hardware. This is made possible by storing m-bit addresses as N-bit entities in sign-extended form and requiring that the results of address computations on these entities be in sign-extended form.

Backward-compatible computer architecture with extended word size and address space

A dual privilege level coprocessor which is especially suited for use in a software asset protection system is described. The coprocessor includes a supervisor processing element and an application processing element. The supervisor processing element includes a supervisor processor and dedicated supervisor random access and read only memory. The application processing element includes an application processor, an application random access memory, a secure random access memory, a low privilege read only memory, and a high privilege read only memory. An internal bus couples the supervisor processor, application processor, high and low privilege random access memories, application random access memory and secure random access memory. The high privilege read only memory and the secure random access memory are enabled only in response to dedicated control signals from the supervisor processor. While the application processor in combination with the low privilege random access memory has many general purpose computing capabilities, it is incapable of executing input or output operations. An input/output device is also coupled to the bus and controlled by the supervisor processor. The secure random access memory is provided for storage of sensitive information such as decryption keys. The coprocessor implements a low privilege level of operation for the purpose of executing protected software which is first decrypted under the control of the supervisor processor and then stored in the application processor random access memory. The coprocessor is also capable of high privilege operation either by the supervisor processor alone or with the supervisor processor controlling the application processor.

Implementing privilege on microprocessor systems for use in software asset protection

The present invention is directed generally to dynamically-selectable vector register partitioning, and more specifically to a processor infrastructure (e.g., co-processor infrastructure in a multi-processor system) that supports dynamic setting of vector register partitioning to any of a plurality of different vector partitioning modes. Thus, rather than being restricted to a fixed vector register partitioning mode, embodiments of the present invention enable a processor to be dynamically set to any of a plurality of different vector partitioning modes. Thus, for instance, different vector register partitioning modes may be employed for different applications being executed by the processor, and/or different vector register partitioning modes may even be employed for use in processing different vector oriented operations within a given applications being executed by the processor, in accordance with certain embodiments of the present invention.

Dynamically-selectable vector register partitioning

The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.

Multiple data channel memory module architecture

A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access). A memory interleave system is provided to optimize the interleaving across the system's memory banks to minimize hot spots resulting from the cache-block oriented and non-cache-block oriented accesses of the heterogeneous computing system.

Memory interleave for heterogeneous computing

A data processing system having an arithmetic unit is designed for a multiplication of n-place numbers in 2's complement according to the Booth algorithm, and for division of unsigned numerals. A 2n-stage shift register is connected over a logical control circuit to the operation code inputs of an ALU. The control circuit automatically forms instruction code signals to the ALU as a function of informational bits derived from the shift register, whereas other operation code input signals are directly connected to the operation code inputs. The control circuit is a sequential circuit having a multiplexer for the selective through-connection of the multiplication code signals, the division code signals, or other operation code signals to the operation code inputs of the ALU.

Data processing system

INSTALLATION POUR LE TRAITEMENT DE DONNEES. LE CIRCUIT DE COMMANDE LOGIQUE 1 EST REALISE SOUS LA FORME D'UNE LOGIQUE SEQUENTIELLE DE MULTIPLICATION-DIVISION, QUI EST RELIEE PAR UNE PREMIERE ENTREE 14 AVEC UN EMPLACEMENT DE REGISTRE 12 DU REGISTRE A DECALAGE SR ET PAR L'INTERMEDIAIRE D'UNE SECONDE ENTREE 15, 16 A UN REGISTRE AUXILIAIRE HR A UN CHIFFRE ET RELIE A CELLE-CI; LE CIRCUIT DE COMMANDE LOGIQUE 11 COMPORTE UN MULTIPLEXEUR 31 A 38 QUI SERT A FAIRE PASSER, PAR SES SORTIES AUX ENTREES DES CODES D'OPERATIONS, LES SIGNAUX D'UN CODE DE MULTIPLICATION, LES SIGNAUX D'UN CODE DE DIVISION, OU DES SIGNAUX D'AUTRES CODES D'OPERATIONS. APPLICATION AUX TRAITEMENTS DES DONNEES.

Pomper Michael

Papers

Data processing system

Installation pour le traitement de donnees