This paper presents design and implementation of Analog Data Acquisition System based on Field Programming Gate Array and 12 bit Analog Digital Conversion Chip ADC128S002. Research presents soft core Universal Asynchronous Receiver Transmitter (UART) model and an additional soft core acquisition model to transmit acquired data at high data baud rate. This paper mostly focused on hardware design and system architecture. Acquisition system is developed using Very high speed integrated circuit Hardware Description Language (VHDL). This system is able to provide converted digital data to the external environment through serial data communication at baud rate 115200. In association this design leaves a choice to configure a maximum number of channels at run time through application protocol which will be used by the controller periodically.

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Design and Synthesis of A FPGA Based Controller Dependent Analog Data Acquisition System

UART (Universal Asynchronous Receiver Transmitter) is used for short-distance, low speed, low-cost data exchange between computer and peripheral. They provide a means to send data with a minimum of wires. The data is sent bit-serially, and no clock signal is sent along with it. The fact that a clock is not transmitted with the data complicates the design of a UART. The two systems (sender and receiver) have separate, unsynchronized, clock signals. The programmable logic devices can be used for such application by developing core for UART. By using hardware descriptive language UART simulation can be tested before it can be loaded on programmable device. In this project we present UART which includes three modules which are the baud rate generator, receiver and transmitter.

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Pratik Kanani

Papers

UART Designing for Four Different Baud Rate for Cyclone III Family