There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

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Low-Voltage Tunnel Transistors for Beyond CMOS Logic

Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1–10 nA/ \({{\mu }}\) m. A common approach to TFET characterization is proposed to facilitate future comparisons.

Tunnel Field-Effect Transistors: State-of-the-Art

Rapid digital technology advancement has resulted in a tremendous increase in computing tasks imposing stringent energy efficiency and area efficiency requirements on next-generation computing. To meet the growing data-driven demand, in-memory computing and transistor-based computing have emerged as potent technologies for the implementation of matrix and logic computing. However, to fulfil the future computing requirements new materials are urgently needed to complement the existing Si complementary metal–oxide–semiconductor technology and new technologies must be developed to enable further diversification of electronics and their applications. The abundance and rich variety of electronic properties of two-dimensional materials have endowed them with the potential to enhance computing energy efficiency while enabling continued device downscaling to a feature size below 5 nm. In this Review, from the perspective of matrix and logic computing, we discuss the opportunities, progress and challenges of integrating two-dimensional materials with in-memory computing and transistor-based computing technologies. This Review discusses the recent progress and future prospects of two-dimensional materials for next-generation nanoelectronics.

Two-dimensional materials for next-generation computing technologies.

We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation It produces steep subthreshold swing (SS) of 46mV/dec and high I ON /I OFF ratio (∼108) and the experiment was successfully repeated after two months Its superior operation is explained through simulation For the first time convincing statistical evidence of sub-60mV/dec SS is presented More than 30% of the devices show sub-60mV/dec SS after systemic data quality checks that screen out unreliable data

Si tunnel transistors with a novel silicided source and 46mV/dec swing

Well designed tunneling green transistor may enable future VLSIs operating at 0.1V. Sub-60mV/decade characteristics have been convincingly demonstrated on 8″ wafers. Large I ON at low V DD are possible according to TCAD simulations but awaits verification. V DD scaling will greatly benefit from low (effective) band gap energy, which may be provided by type II heterojunctions of Si/Ge or compound semiconductors.

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Prospect of tunneling green transistor for 0.1V CMOS

IC power consumption is not only a package thermal issue but also a significant and fast growing part of the world electricity consumption. A new low voltage transistor could contribute greatly to the need for a new Vdd scaling scenario. Green transistor (gFET) is based on tunneling and provides Ion and Ioff far superior to MOSFET at 0.2 V if suitable low-Eg material is introduced into IC manufacturing.

Green Transistor - A V DD Scaling Path for Future Low Power ICs

A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.

Low-voltage green transistor using ultra shallow junction and hetero-tunneling

—A new tunneling transistor structure is introduced that offers several advantages over prior designs. Notably, tunneling area is substantially increased. Turn on/off swing is improved by engineering doping profile to ensure tunneling initiates in high electric field region. TCAD simulations explore the critical design considerations. The concept of heterojunction tunneling is introduced as a means to achieve low effective band gap and low voltage operation for the design in consideration. I. I NTRODUCTION Increasing power consumption presents a major problem for future ICs. A transistor that can operate below 0.5 V supply is highly desirable. Maintaining large I on /I off ratio at such low V dd is a challenge for MOSFET given the 60 mV/decade subthreshold swing limit. This limit governs the turn off/on of any device based on flow of carriers over an energy barrier. Band-to-band tunneling (BTBT) is one process not subject to this limitation. Researchers have long explored the BTBT transistor [1-2]. However, all have relied on the same basic structure -- the gated PN diode. This conventional structure for an n-type FET is shown in Fig. 1. The location of tunneling is indicated by the arrow at the edge of the source region. The transistor “turns on” when the gate voltage exceeds the overlap voltage, V

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Pratik Patel

Papers

Si tunnel transistors with a novel silicided source and 46mV/dec swing

Prospect of tunneling green transistor for 0.1V CMOS

Green Transistor - A V DD Scaling Path for Future Low Power ICs

Low-voltage green transistor using ultra shallow junction and hetero-tunneling

A Low Voltage Steep Turn-Off Tunnel Transistor Design