The present disclosure includes a three dimensional (3D) integrated device comprising a first die having a first supply line and a second die having a second supply line, a power header, and voltage selection logic The power header is connected to the first die and the second die and configured to generate a first voltage on a first voltage line and a second voltage on a second voltage line The voltage selection logic is connected to the first supply line and the second supply line and configured to select between the first voltage line and the second voltage line for each of the first supply line and the second supply line

Power delivery to three-dimensional chips

We present an IR-drop analysis of hybrid bonded 3D-ICs Power Delivery Network with backside metals and buried power rail. Two different options for the backside to frontside connectivity are included: μTSVs and nTSVs (respectively 0.5μm, 0.09μm diameter and 1Ω, 10Ω nominal resistance). Further, Hybrid Bonding CuPads are used to deliver power to the second die in the stack. A commercial power analysis tool is extended to support both the TSV and the pads structures, to tackle both inter-die and on-die power delivery challenges. A L1 cache memory implemented on the top of a core is used as test case to assess the performance of the proposed metal stack. A 69% reduction in average static IR-drop is observed with the BS-PDN compared to the conventional frontside. Further, 81% and 77% average and peak IR-drop reductions are obtained with nTSV compared to μTSV.

IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and μ- & n- TSVs

Power integrity is generally considered to be one of the major bottlenecks hindering the prevalence of three-dimensional integrated circuits (3D ICs). The higher integration density and smaller footprint result in significantly increased power density, which threatens the system reliability. In view of this, there has been groundswell of interest in academia to model, design or optimize the power delivery networks (PDNs) in 3D ICs. Unfortunately, while several PDN benchmarks exist for 2D PDNs, none is available in the context of 3D. As a consequence, most existing literature resorts to ad-hoc designs by artificially stacking 2D PDNs for experiments, rendering the results less convincing. In this paper, we put forward a set of ten PDN benchmarks that are extracted from industrial 3D designs. These designs are carefully selected such that they cover a wide range of functionality, size, TSV number, tier number and packaging style. We hope that the released benchmarks can facilitate and promote research in 3D PDNs.

Benchmarking for research in power delivery networks of three-dimensional integrated circuits

This paper proposes a method to reduce the supply voltage IR drop of 3D stacked-die systems by implementing an on-chip Buck Converter on Top die (BCT) scheme. The IR drop is caused by the parasitic resistance of Through Silicon Vias (TSV's) used in the 3D integration. The IR drop reduction and the overhead associated with the BCT scheme are modeled and analyzed. A 3D stacked-die system is manufactured using 90nm CMOS technology with TSV's and a silicon interposer. A chip inductor and chip capacitors for the buck converter are mounted directly on the top die. The reduction of the IR drop to less than 1/4 is verified through experiments.

Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme

In this paper, two topics about an on-chip DC-DC buck converter are described. First, the buck converter with an inductor on interposer is investigated for mobile applications. Simulation results indicate that the efficiency of the buck converter is improved by introducing a ferrite film to the inductor. Next, a circuit technique to reduce IR drop in 3D stacked integration using the buck converter is proposed. In this paper, 3D stacked-die system, which consists of stacked dies and silicon interposer, is fabricated and measurement results show that the proposed technique achieves 78% decrease in IR voltage drop compared with the conventional approach.

On-chip buck converter with spiral ferrite inductor and reducing IR drop in 3D stacked integration

Power delivery network (PDN) design is already a challenging problem for single die designs using advanced process technologies. For systems created using stacked dies with TSVs, several additional issues that affect power delivery and reliability have to be addressed. In stacked die configuration, the dies higher up in the stack-up experience additional drop and noise in their power supply as it propagates through the TSV networks of one or more dies placed lower in the stack-up. For the lower dies, the presence of the TSV farm and associated metals/vias affects the homogeneity of their own power delivery network. And if multiple dies share power and ground domains, then there could be an inter-die propagation of supply noise. So it becomes important that a PDN design and optimization flow for stacked die designs models and analyzes the presence of multiple dies and also the switching and the noise impact from the dies on each other. The analysis could be concurrent or model based, depending upon whether full databases for all the chips are available or their electrically equivalent models such as Chip Power Model (CPM) are available, respectively. For both of these approaches, a DC and time-domain analysis has to be done at the chip layout level to accurately predict the power/ground noise in the stacked die design. These analyses need to done starting early, in order to enable prototyping and design trade-off decisions. In this paper, a prototyping and verification solution for multi-die TSV based designs is outlined along with results from various design decisions undertaken.

Pratyush Singh

Papers

Power delivery network design and optimization for 3D stacked die designs