. Wireless communication is a fast-growing industry and recent developments focus on improving certain aspects of the area and reducing the power consumption while maintaining the frequency of operation. Phase Locked Loop (PLL) is an integral part of communication circuits which operate at very high frequencies. Phase Frequency Detector (PFD) is the first block of PLL and is key in determining the computational capacity of the PLL. The power consumption of the PFD has to be reduced to minimize the overall power consumption of PLL. The PFD architecture used is based on Double Edged Triggered D Flip-Flop (DET-DFF), which is free of dead zone. Stack, LECTOR, AVLS and hybrid low-power approaches are implemented to reduce the power consumption of DET-DFF based PFD architectures. The PFDs power, delay and power delay product analysis is performed using Cadence Virtuoso and Spectre in CMOS 180 nm and 90 nm technology. A power reduction of upto 32 % has been observed while keeping the transistor count to a minimum.

Low-Power Phase Frequency Detector Using Hybrid AVLS and LECTOR Techniques for Low-Power PLL

Phase lock loop (PLL) operates at higher frequency and due to the increased switching, the power consumed is high. The increase in demand of applications in communications systems has led to fully integrated, minimal power and high performance PLL. There is a demand for low power applications and hence various methods have been emerging. The power of the PLL has to be reduced and optimized by reducing the power of all the sub-blocks of PLL. Adaptive voltage level (AVLS) technique is incorporated in the circuit to reduce power consumption. The phase detector of the PLL is replaced with a phase frequency detector with dead zone which is used to reduce the power of the PLL. The number of transistors is also reduced thereby reducing the area of the PLL. Also MOSFETs are used for the design of loop filter. The circuits are realized using CMOS 180nm technology in Cadence Virtuoso and simulated using Cadence Spectre. Proposed modified PLL architecture's is compared w.r.t. reference PLL architectures at various frequencies. Proposed PLL architectures consumes very less power compared to reference PLL architectures even at higher frequency (>1 GHz).

PFD with Dead zone based Low Power Modified Phase Lock Loop using AVLS Technique

Cyber Physical Systems (CPS) is essential for the integration of the physical world with the virtual electronic world. The only way to provide security to these constrained environment applications is through Lightweight Cryptography. To provide stronger security, with elevated performance and less power consumption, two PRESENT architectures are proposed in this paper. The first architecture provides the option to choose one of the three MEC S-boxes, whereas the second architecture makes use of a single MEC S-box to provide better security and increased performance for encryption and decryption processes. The Standard S-box is replaced with MEC S-box, which has its own advantages, such as, less power consumption, linear time and constant space complexity. To analyse the various parameters of the proposed architectures, they are synthesized using Xilinx Virtex-7 FPGA, in Xilinx Vivado IDE. With respect to Strict Avalanche Criterion (SAC), the standard usage of S-box, nearly gives 50% SAC whereas, at least two orders of MEC S-boxes used in the proposed architectures give more than 50% SAC for the entire algorithm, thereby increasing the security of the whole process. The results depict that the proposed architecture provides a throughput of 1564.02 Mbps whereas with a lesser power consumption.

Premananda B. S

Papers

PFD with Dead zone based Low Power Modified Phase Lock Loop using AVLS Technique

MEC S-box based PRESENT Lightweight Cipher for Enhanced Security and Throughput