This paper contains the performance analysis of various available designs of full adders It is observed that the full adder is designed for 1 bit, and later it is extended for 32 bits also The circuit is designed by using 180 nm technology at 18 V supply and technology using 90 nm at 12 V supply using Cadence Virtuoso tools High speed, low consumption of power, better power–delay product (PDP), layout area, better propagation delay, these are the performance parameters that are compared for various full adders The circuit performs better in case of improvement of the full adder circuit in terms of parameters like speed and power

Analysis on High-Performance Full Adders

Comprehensive Analysis of a Power-Efficient 1-Bit Hybrid Full Adder Cell

An On the Fly Conversion Technique included array multiplier with optimum design. A multiplier loaded with N-Bit results to produce 2N bit partial products. The discrimination of bits will be as (2N) -(N/2) in addition with N/2 Bits. The arrangement of the bits differed with each other depending on the positions in their structure. This paper is considered in implementing an array multiplier using On the Fly Conversion Technique staked with Hybrid Full Adders which reduces the time delay. Instead of using a truncation or addition approach, the array multiplier described in this paper is implemented using a standard array multiplier scheme. The OTFC Logic Is used to boost Carry-Propagation at the final stage of Multiplication. The OFTC inputs were irrespective of the number of input bits. To incorporate the MSB bits in parallel with the LSB bits, all of the final carry outputs were added into the OFTC circuit to get the result in less time. The Full Adders loaded in the Multiplier Designed Using PTL and CMOS Logic resulted in remarkable decrease in the time delay.

VLSI IMPLEMENTATION OF A HIGH SPEED MULTIPLIER USING ON THE FLY CONVERSION TECHNIQUE: On the fly conversion technique

This paper proposes a novel fusion 1bit Adder/Subtractor design using the CMOS transistor. The proposed novel fusion 1 bit Adder/Subtractor is utilized in the design of parallel adder/subtractor with the resolution upto 27 bits. Though there are several design technologies like static CMOS logic, Dynamic CMOS, CPL, Transmission Gate Array, the proposed Fusion Design is advantageous for minimized chip area, low power consumption and high speed of operation. In this work, two circuit topologies are proposed by utilizing the 8T and 12T XOR CMOS design for the novel Fusion Adder/Subtractor. This paper compares the parametric values of power, delay and area with the existing methods. The proposed design is developed using the Cadence Virtuoso Tool with the technology of 45 nm. The proposed fusion design exhibits low power and delay as the resolution of the design is increased. Also the chip area is 0.3138µm2 for the 28T FAS circuit and 0.165 µm2 for the proposed 24T FAS circuit.

Performance Analysis of a novel Fusion Adder/Subtractor design

In Digital Circuits the core component of the Arithmetic logic unit (ALU) is an adder which can perform arithmetic operations thus adders play an essential role in the digital VLSI System. In modern VLSI systems, the entire research moves towards low power and nanotechnology to make the performance of the digital system excellent. The proposed circuit is formed utilizing a hybrid design approach which includes conventional complementary metal-oxide semiconductors, transmission gates and pass transistors (PTs) (C-CMOS). The proposed architecture of hybrid Full Adder (FA) is superior to the existing FA in both power and overall PDP but delay is not much improved. The proposed hybrid FA design architecture is investigated using 90nm technology node on Cadence virtuoso tool. Due to its lower power consumption and optimized value of power delay product, the simulation results proved that the hybrid FA performance analysis is superior and energy efficient. Power Consumption by the proposed single bit hybrid FA is 0.425 watt at the 0.8V supply voltage and input frequency of 100MHz. The proposed design of 1-bit hybrid adder is analyzed at various supply voltage at 90nm technology node with improved performance in both Power delay product (PDP) and power.

Design and Performance Analysis of 18T Low Power 1-bit Hybrid Full Adder

The paper presents a new model of low power 1-bit hybrid adder that uses CMOS and Transmission gate technologies together and produces full swing outputs. This adder is compared with the existing Conventional-CMOS (C-CMOS), CPL, TGA, 14T, 24T hybrid adder and 16T hybrid adder in terms of power, delay and power-delay product in 180-nm and 65-nm technology. The simulations were carried on for different voltages and frequencies on the Cadence Virtuoso using the Spectre simulator. The results conclude that the proposed adder consumes 35–40% low power compared to C-CMOS and is 25–50% faster than C-CMOS.

Priya Agrawal

Papers

A low-power high-speed 16T 1-Bit hybrid full adder