Line-edge roughness induced fin-edge roughness (FER) is the primary source of $V_{T}$ variation in FinFETs. Conventionally, stochastic simulations are performed to predict the device variability due to FER for a technology, which are computationally expensive. An analytical formulation to predict variability due to FER enables understanding of the effect of input parameters as well as provides quantitative results at fractional computational costs. In this paper, we develop and present an analytical model to estimate saturation $V_{T}$ ( $V_{{T\rm {-sat}}})$ variability due to FER. The model is capable of capturing the $V_{T}$ variability dependence on device parameters ( $L_{G}$ and $W_{\mathrm{ fin}}$ ) and variability parameters (correlation length $\Lambda $ and standard deviation $\Delta )$ accurately. The entire $V_{{T\rm {-sat}}}$ distribution obtained by the model is also presented and compared against the $V_{{T\rm {-sat}}}$ distribution of stochastic simulations to show that the model captures the distribution effectively. We show that not only $\sigma V_{T}$ but even $\mu V_{T}$ is affected by variability parameters. Hence, such modeling is critical to defining nominal FinFET structure ( $L_{G}$ and $W_{\mathrm{ fin}}$ ), which is affected by variability ( $\Lambda $ and $\Delta $ ) especially for scaled FinFETs, where quantum-confinement effects are enhanced.

An Analytical Model to Estimate FinFET’s $V_{T}$ Distribution Due to Fin-Edge Roughness

In our earlier work, we presented a percolation theory-based analytical model to estimate FinFET’s ${V}_{T}$ distribution due to fin edge roughness. The earlier models in the literature were based on minimum fin width, the limitations of which were discussed in detail. In this paper, we advance the percolation theory-based model to capture the variability in all key-device parameters, viz. ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ , subthreshold slope, and ${V}_{T}$ . The entire distribution of these parameters obtained by the model is presented and compared against stochastic TCAD to demonstrate excellent match. The model reduces rms error in $\mu $ of various parameters by 5%–60%, and 20%–50% in $\sigma $ with respect to the minimum fin width-based models present in the literature.

Analytical Model to Estimate FinFET’s ${\text I}_{\text {ON}}$ , ${\text I}_{\text{OFF}}$ , SS, and ${\rm V}_{T}$ Distribution Due to FER

Line edge roughness (LER) is a critical variability source in scaled FinFETs. LER produces line width roughness (LWR) that causes threshold voltage ( ${V}_{T}$ ) variability. Various lithography techniques demonstrate characteristic LER-LWR relationship. For translating LER/LWR to the ${V}_{T}$ distribution, an analytical model for uncorrelated fin edges (correlation coefficient, $\rho ={0}$ ) has been presented in the literature. However, a range of correlation coefficients ( ${0}\le \rho \le {0.85}$ ) between two fin edges is experimentally observed for various lithography techniques. In this paper, we present an analytical model to predict $\rho $ dependent ${V}_{T}$ distribution for partially correlated fin edges in FinFETs. First, an analytical model of mean ( $\mu $ ) and standard deviation ( $\sigma $ ) for $\rho $ dependent minimum, maximum, and average fin width is presented. This is used to construct an equivalent simplified trapezoidal fin distribution. Second, percolation theory-based model is used to compute ${V}_{T}$ distribution from the fin distribution. The model is validated against well-calibrated TCAD simulations for a wide range of geometrical (channel length ${L}_{G}$ and nominal fin width ${W}_{\text {fin}})$ and LER variability (correlation length $\Lambda $ and correlation coefficient $\rho $ ) parameters to show excellent match. The model is 1000 times faster compared with TCAD simulations.

An Analytical Model to Estimate ${V}_{T}$ Distribution of Partially Correlated Fin Edges in FinFETs Due to Fin-Edge Roughness

Process-induced variation (PIV) is the major bottleneck for using advanced CMOS technology efficiently. Even though the multigate nature of the fin field effect transistor (FinFET), nano-wire FET (NWFET), and nanosheet FET (NSFET) make the device robust toward the short channel effects (SCEs), unpredictable device-to-device variation caused by unwanted PIV remains a challenge for the designers. In this article, we propose a generic variability model to describe the impact of PIV on performance parameters of advanced devices. The major focus of this article is to demonstrate two independent analytical models capturing the impact of metal gate granularity (MGG) and line edge roughness (LER) on the threshold voltage ( V T ) of FinFET. The proposed model is not only limited to the variability estimation of V T , but also capable of estimating the on-current ( I on), subthreshold slope (SS), and off-current ( I off) distribution due to LER accurately. Both the models are generic enough to be extended to be used for NWFET, and NSFET, and utilizes simple physics and mathematics, therefore, it can be implemented in any platform. The models are 100-1,000 times faster in comparison to the technology CAD (TCAD) simulations, and accuracy is on par with the TCAD results. Such models, when integrated with the existing nominal SPICE setup, the circuit-level performance prediction will be comparable to the experimental results. As the models take process-generated variations as an input to produce corresponding performance variation, it will further enable the co-optimization of the process as well as the circuit performance.

Nanoscale Transistor Variability Modeling: How Simple Physics Enables a Powerful Prediction Platform

We report the first compact model to estimate the ${V}_{T}$ distribution of double gate-FinFET due to line edge roughness. We derive closed-form expressions, representing the compact model, for: 1) mean and standard deviation of fin width ( ${W}_{\text {fin}}$ ) in terms of geometrical and variability parameters of the FinFET; 2) ${V}_{T}$ as a function of ${W}_{\mathrm {fin}}$ for uniform width fins; and 3) ${V}_{T}$ in tapered fins using percolation. The ${V}_{T}$ distribution produced from the compact model shows a good match with well-calibrated TCAD data and demonstrates an excellent accuracy (~3mV rms error) for a wide range of scaling and variability parameters. The model is simple, platform independent, and $\sim {\text {10}}^{\text {4}}{\times }$ faster compared to TCAD. It enables intuitive understanding of design space for FinFET on the one hand, and accurate FinFET variability-aware circuits and system design on the other hand.

The First Compact Model to Determine $V_{T}$ Distribution for DG-FinFET Due to LER

In this paper, we have proposed a computationally efficient method to evaluate threshold voltage (V T ) variability due to Line Edge Roughness (LER) in sub-20nm node FinFETs. For channel lengths less than 15 nm, the variability in threshold voltage may be estimated to a great accuracy (error T from LER specifications of a fin patterning technology.

http://ieeexplore.ieee.org/iel7/6917163/6931540/06931617.pdf

Punyashloka Debashis

Papers

A FinFET LER V T variability estimation scheme with 300× efficiency improvement