Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed and ii) proposing a reconfigurable NoC-based turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm2 and a power consumption of 101.5 mW in the worst case.

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VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture

To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA +/LTE/LTE-Advanced multi-standard turbo decoder with a 45 nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm 2. When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards.

Parallel Interleaver Design for a High Throughput HSPA $+$ /LTE Multi-Standard Turbo Decoder

In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction. However, owing to the serial data dependencies imposed by the underlying logarithmic Bahl–Cocke-Jelinek–Raviv (Log-BCJR) algorithm, the limited processing throughputs of conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time wireless communication schemes. Motivated by this, we recently proposed a fully parallel turbo decoder (FPTD) algorithm, which eliminates these serial data dependencies, allowing parallel processing and hence offering a significantly higher processing throughput. In this paper, we propose a novel resource-efficient version of the FPTD algorithm, which reduces its computational resource requirement by 50%, which enhancing its suitability for field-programmable gate array (FPGA) implementations. We propose a model FPGA implementation. When using a Stratix IV FPGA, the proposed FPTD FPGA implementation achieves an average throughput of 1.53 Gb/s and an average latency of 0.56 $\mu \text{s}$ , when decoding frames comprising ${N}=720$ b. These are, respectively, 13.2 times and 11.1 times superior to those of the state-of-the-art FPGA implementation of the Log-BCJR long-term evolution (LTE) turbo decoder, when decoding frames of the same frame length at the same error correction capability. Furthermore, our proposed FPTD FPGA implementation achieves a normalized resource usage of 0.42 (kALUTs/Mb/s), which is 5.2 times superior to that of the benchmarker decoder. Furthermore, when decoding the shortest $N=40$ -b LTE frames, the proposed FPTD FPGA implementation achieves an average throughput of 442 Mb/s and an average latency of 0.18 $\mu \text{s}$ , which are, respectively, 21.1 times and 10.6 times superior to those of the benchmarker decoder. In this case, the normalized resource usage of 0.08 (kALUTs/Mb/s) is 146.4 times superior to that of the benchmarker decoder.

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

Quasi-cyclic low-density parity-check (QC-LDPC) codes are the choice for data channels in the fifth generation (5G) new radio (NR). At the transmitter side, code bits from the QC-LDPC encoder are delivered to the rate matcher. The task of the rate matcher is to select an appropriate number of code bits via puncturing and/or repetition. Code bits that are not selected do not need to be encoded. At the receiver side, the de-rate matcher combines code bits of different transmission attempts and sends them to the QC-LDPC decoder. The output of the QC-LDPC decoder only needs to include necessary systematic bits. Unnecessary systematic bits and parity bits can be completely removed from the decoding process. Taking these considerations into account, a smaller sub-base matrix instead of a full-base matrix can be used in the encoding and decoding process. In this paper, we propose an efficient implementation of QC-LDPC codes for 5G NR. The full-base matrix is pruned before being used. Compared to the traditional schemes, the proposed scheme improves the throughput of QC-LDPC codes in 5G NR.

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A High Throughput Implementation of QC-LDPC Codes for 5G NR

The current convergence process in wireless technologies demands for strong efforts in the conceiving of highly flexible and interoperable equipments. This contribution focuses on one of the most important baseband processing units in wireless receivers, the forward error correction unit, and proposes a Network-on-Chip (NoC) based approach to the design of multi-standard decoders. High level modeling is exploited to drive the NoC optimization for a given set of both turbo and Low-Density-Parity-Check (LDPC) codes to be supported. Moreover, synthesis results prove that the proposed approach can offer a fully compliant WiMAX decoder, supporting the whole set of turbo and LDPC codes with higher throughput and an occupied area comparable or lower than previously reported flexible implementations. In particular, the mentioned design case achieves a worst-case throughput higher than 70 Mb/s at the area cost of 3.17 mm2 on a 90 nm CMOS technology.

A network-on-chip-based turbo/LDPC decoder architecture

In order to address the large variety of channel coding options specified in existing and future digital communication standards, there is an increasing need for flexible solutions. This paper presents a multi-core architecture which supports convolutional codes, binary/duo-binary turbo codes, and LDPC codes. The proposed architecture is based on Application Specific Instruction-set Processors (ASIP) and avoids the use of dedicated interleave/deinterleave address lookup memories. Each ASIP consists of two datapaths one optimized for turbo and the other for LDPC mode, while efficiently sharing memories and communication resources. The logic synthesis results yields an overall area of 2.6mm2 using 90nm technology. Payload throughputs of up to 312Mbps in LDPC mode and of 173Mbps in Turbo mode are possible at 520MHz, fairing better than existing solutions.

A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding

Emerging wireless digital communication standards specify a large variety of channel coding options, each suitable for specific application needs. In this context, several recent efforts are being conducted to propose flexible channel decoder implementations. However, the need of optimal solutions in terms of performance, area, and power consumption is increasing and cannot be neglected against flexibility. In this paper we present a novel parameterized architecture for multi-standard Turbo decoding which illustrates how flexibility, architecture efficiency, and rapid design time can be combined. The proposed architecture supports both single-binary Turbo codes (SBTC) of 3GPP-LTE and double-binary Turbo codes (DBTC) of WiMAX and DVB-RCS standards. It achieves, in both modes, a high architecture efficiency of 4.37 bits/cycle/iteration/mm2. A major contribution of this work concerns the rapid design time allowed by the well established design concept and tools of application-specific instruction-set processors (ASIPs). Using such a tool, the paper illustrates the possibility to design application-specific parameterized cores, removing the need of the program memory and the related instruction decoder.

Parameterized area-efficient multi-standard turbo decoder

In order to address the large variety of channel coding options specified in existing and future digital communication standards, there is an increasing need for flexible solutions. Recently proposed flexible solutions in this context generally presents a significant area overhead and/or throughput reduction compared to dedicated implementations. This is particularly true while adopting an instruction-set programmable processors, including the recent trend toward the use of Application Specific Instruction-set Processors (ASIP). In this paper we illustrate how the application of adequate algorithmic and architecture level optimization techniques on an ASIP for turbo decoding can make it even an attractive and efficient solution in terms of area and throughput. The proposed architecture integrates two ASIP components supporting binary/duo-binary turbo codes and combines several optimization techniques regarding pipeline structure, trellis compression (Radix4), and memory organization. The logic synthesis results yield an overall area of 1.5mm2 using 90nm CMOS technology. Payload throughputs of up to 115.5Mbps in both double binary Turbo codes (DBTC) and single binary (SBTC) are achievable at 520MHz. The demonstrated results constitute a promising trade-off solution between throughput and occupied area comparing with existing implementations.

Area and throughput optimized ASIP for multi-standard turbo decoding

Hardware prototyping has been the key to system validation, once the hardware simulation matches the software model results and before the final silicon tape-out. On the other hand, flexible multi-standard implementations are being widely investigated these last years for the challenging channel decoding application. The latest contributions explore ASIP (Application-Specific Instruction-set Processor) concept and target to achieve efficient resource sharing between advanced Turbo and LDPC iterative decoders. In this paper we present an FPGA-based prototype of a multistandard Turbo/LDPC Encoding and Decoding. The functional prototype implements a full communication system including encoder, channel model, ASIP-based decoder and performance counters. All components are flexible and are dynamically configurable through a dedicated GUI (Graphical User Interface). The prototype supports all communication modes defined in LTE, WiFi, WiMAX, and DVB-RCS wireless communication standards.

FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding

Many modern and emerging designs require having efficient dynamically reconfigurable and reprogrammable processors. However, when the implemented design needs an upgrade, newly added features have to be quickly supported and validated. This is clearly noticed in modern receivers of recent wireless communication standards that feature continuously different frame lengths and code rates for the channel decoder. This paper explores with an example the possibility of realizing a flexible channel decoder to implement and validate new/incremental algorithm changes with fast turnaround time in design. An application specific instruction-set processor (ASIP) is proposed as flexible core that can decode low-density parity-check (LDPC) codes with the various block sizes and code rates as specified in WiFi and WiMAX standards. Furthermore, the proposed architecture enables quick support of other Quasi-Cyclic LDPC (QC-LDPC) codes, e.g. DVB-S2, with simple incremental hardware changes at design time.

Purushotham Murugappa

Papers

A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding

Parameterized area-efficient multi-standard turbo decoder

Area and throughput optimized ASIP for multi-standard turbo decoding

FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding

Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes