METIS is the EU flagship 5G project with the objective of laying the foundation for 5G systems and building consensus prior to standardization. The METIS overall approach toward 5G builds on the evolution of existing technologies complemented by new radio concepts that are designed to meet the new and challenging requirements of use cases today?s radio access networks cannot support. The integration of these new radio concepts, such as massive MIMO, ultra dense networks, moving networks, and device-to-device, ultra reliable, and massive machine communications, will allow 5G to support the expected increase in mobile data volume while broadening the range of application domains that mobile communications can support beyond 2020. In this article, we describe the scenarios identified for the purpose of driving the 5G research direction. Furthermore, we give initial directions for the technology components (e.g., link level components, multinode/multiantenna, multi-RAT, and multi-layer networks and spectrum handling) that will allow the fulfillment of the requirements of the identified 5G scenarios.

Scenarios for 5G mobile and wireless communications: the vision of the METIS project

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[서평]「Computer Organization and Design, The Hardware/Software Interface」

We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the edge of congestion. Typical applications are in the area of multi-media processing. We consider a mesh-based networks on chip (NoC) architecture, and we explore the assignment of cores to mesh cross-points so that the traffic on links satisfies bandwidth constraints. A single-path deterministic routing between the cores places high bandwidth demands on the links. The bandwidth requirements can be significantly reduced by splitting the traffic between the cores across multiple paths. In this paper, we present NMAP, a fast algorithm that maps the cores onto a mesh NoC architecture under bandwidth constraints, minimizing the average communication delay. The NMAP algorithm is presented for both single minimum-path routing and split-traffic routing. The algorithm is applied to a benchmark DSP design and the resulting NoC is built and simulated at cycle accurate level in SystemC using macros from the /spl times/pipes library. Also, experiments with six video processing applications show significant savings in bandwidth and communication cost for NMAP algorithm when compared to existing algorithms.

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Bandwidth-constrained mapping of cores onto NoC architectures

MTC are expected to play an essential role within future 5G systems. In the FP7 project METIS, MTC has been further classified into mMTC and uMTC. While mMTC is about wireless connectivity to tens of billions of machinetype terminals, uMTC is about availability, low latency, and high reliability. The main challenge in mMTC is scalable and efficient connectivity for a massive number of devices sending very short packets, which is not done adequately in cellular systems designed for human-type communications. Furthermore, mMTC solutions need to enable wide area coverage and deep indoor penetration while having low cost and being energy-efficient. In this article, we introduce the PHY and MAC layer solutions developed within METIS to address this challenge.

Massive machine-type communications in 5g: physical and MAC-layer solutions

http://www.cas.mcmaster.ca/~sancheg/EE_UCU2006_thesis/biblio/Methods%20for%20Evaluating%20and%20Covering%20the%20Design%20Space%20during%20Early%20Design%20Development%20%28ucb-erl_m03-32_DSE_survey%29.pdf

Methods for evaluating and covering the design space during early design development

This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. Component-based design provides primitives to build complex architectures from basic components. This bottom up approach allows design-architects to explore efficient custom solutions with best performances. This paper presents a high-level component-based methodology and design environment for application-specific multicore SoC architectures. The system specifications are represented as a virtual architecture described in a SystemC-like model and annotated with a set of configuration parameters. Our component-based design environment provides automatic wrapper-generation tools able to synthesize hardware interfaces, device drivers, and operating systems that implement a high-level interconnect API. This approach, experimented over a VDSL system, shows a drastic design time reduction without any significant efficiency loss in the final circuit.

/pdf/component-based-design-approach-for-multicore-socs-2oang28hzz.pdf

Component-based design approach for multicore SoCs

We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level system specification. Parameters are used to instantiate architectural components, such as processors, memory modules and communication networks. The flow includes the automatic generation of a communication coprocessor that adapts the processor to the communication network in an application-specific way. Experiments with two system examples show the effectiveness of the presented design flow.

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Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip

Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Besides application algorithm optimizations and application-specific instruction-set processor design, the on-chip communication network constitutes a major issue in this application domain. In this paper, the authors propose to use multistage interconnection networks as on-chip communication networks for parallel turbo decoding. Adapted benes and butterfly networks are proposed with detailed hardware implementation of network interfaces, routers, and topologies. In addition, appropriate packet format and routing for interleaved/deinterleaved extrinsic information exchanges are proposed. The flexibility of these on-chip communication networks enables their use for all turbo code standards and constitutes a promising feature for their reuse for any similar interleaved/deinterleaved iterative communication profile

/pdf/butterfly-and-benes-based-on-chip-communication-networks-for-4kki72rjse.pdf

Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding

In communication refinement with multiple communication protocols and abstraction levels, the system specification is described by heterogeneous components in terms of communication protocols and abstraction levels. To adapt each heterogeneous component to the other part of system, we present a generic wrapper architecture that can adapt different protocols or different abstraction levels, or both. In this paper, we give a detailed explanation of applying the generic wrapper architecture to mixed-level cosimulation. As preliminary experiments, we applied it to mixed-level cosimulation of an IS-95 CDMA cellular phone system.

/pdf/a-generic-wrapper-architecture-for-multi-processor-soc-22ipxugb49.pdf

A generic wrapper architecture for multi-processor SoC cosimulation and design

In this paper, we present a novel approach for the design of application specific multiprocessor systems-on chip. Our approach is based on a generic architecture model which is used as a template throughout the design process. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of applications. In addition, it allows one accelerate the design cycle. This paper focuses on the definition of the architecture model and the systematic design flow that can be automated. The feasibility and effectiveness of this approach are illustrated by two significant demonstration examples.

/pdf/an-efficient-architecture-model-for-systematic-design-of-2704qidlhx.pdf

Amer Baghdadi

Papers

Component-based design approach for multicore SoCs

Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip

Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding

A generic wrapper architecture for multi-processor SoC cosimulation and design

An efficient architecture model for systematic design of application-specific multiprocessor SoC