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Design Of Analog Cmos Integrated Circuits

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. 

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. 

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.




* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.

Three-Dimensional Integrated Circuit Design

Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for two-dimensional circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits while considering different forms of vertical integration, such as system-in-package and 3-D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated in vertical integration due to the limited number of package pins, the distance of these pins from other planes within the 3-D system, and the impedance characteristics of the through silicon vias (TSVs). In addition to these dedicated networks, global signaling techniques that incorporate the diverse traits of complex 3-D systems are required. One possible approach, potentially significantly reducing the complexity of interconnect issues in 3-D circuits, is 3-D networks-on-chip (NoC). Design methodologies that exploit the diversity of 3-D structures to further enhance the performance of multiplane integrated systems are necessary. The longest interconnects within a 3-D circuit are those interconnects comprising several TSVs and traversing multiple physical planes. Consequently, minimizing the delay of the interplane nets is of great importance. By considering the nonuniform impedance characteristics of the interplane interconnects while placing the TSVs, the delay of these nets is decreased. In addition, the difference in electrical behavior between the horizontal and vertical interconnects suggests that asymmetric structures can be useful candidates for distributing the clock signal within a 3-D circuit. A 3-D test circuit fabricated with a 180 nm silicon-on-insulator (SOI) technology, manufactured by MIT Lincoln Laboratories, exploring several clock distribution topologies is described. Correct operation at 1 GHz has been demonstrated. Several 3-D NoC topologies incorporating dissimilar 3-D interconnect structures are reviewed as a promising solution for communication limited systems-on-chip (SoC). Appropriate performance models are described to evaluate these topologies. Several forms of vertical integration, such as system-in-package and different candidate technologies for 3-D circuits, such as SOI, are considered. The techniques described in this paper address fundamental interconnect structures in the 3-D design process. Several interesting research problems in the design of 3-D circuits are also discussed.

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Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits : Vertical integration is a novel communications paradigm where interconnect design is a primary focus

The recent hierarchical design framework[8] for 3D floorplan-ning suggests a better performance than previous flat design framework. Under this framework, the layer assignment of the blocks is accomplished by some partitioning algorithms which are assumed to be critical[8]. In this paper, we provide an empirical study on the impact of such partitioning algorithms on the total wire length. By generating various partitions and running our floorplanner based on these partitions, we obtain the statistic of the resultant wire length. We observe that when the design instance has a large number of blocks which are uniformly sized, different partitions with the same cut size lead to roughly the same wire length. By another experiment, we find out that the cut size of the partition has the major influence on the wire length. Therefore, we argue that cut size is a metric good enough for the wire length optimization of 3D floorplanning and suggest that future research focus on other problems such as thermal effect, signal delay, etc.

How does partitioning matter for 3D floorplanning

This paper addresses the problem of transistor decomposition, which can be used in high accuracy analog applications and structured analog design. We made a test chip to verify the feasibility of the transistor decomposition because of the lack of theoretical support. The DC/AC measurement results from the chip suggests that the decomposition, the transistor channel tuning, as well as structured analog design based on the transistor array are applicable. Also our test chip shows that design with transistor array can suppress the variation of V th stemmed from CMP process. Based on this conclusion, we propose a simple framework with transistor array for structured analog layout generation, which involves the transistor decomposition. Using this framework, we generate several layouts for a typical CMOS OPAMP circuit and compare the automatically generated layouts with the manual layouts. Although the layout sizes of the transistor array based OPAMPs are slightly bigger than that of the manual designs, the automatic layout generation is much faster than manually synthesizing the layout.

Structured analog circuit design and MOS transistor decomposition for high accuracy applications

This paper introduces a new concept of regularity-oriented floorplanning and block placement — structured placement, it takes the regularity as a criterion of placement so as to improve the performance. We provide the methods to extract regular structures from a placement representation in linear time, and manage to evaluate these structures by quantifying the regularity as an objective function. We also construct a particular simulated annealing framework, which optimizes placement topology and physical dimension separately and alternately so that it attains a solution balancing the trade-off between regularity and area efficiency. Furthermore, we introduce the symmetry-oriented structured placement to produce symmetrical placement. Experiments show that the resultant placements achieve regularity without increased chip area and wire length, compared to those by existing methods.

Structured Placement with Topological Regularity Evaluation

In this letter, a new efficient model pruning method, called regularized sparsity adaptive matching pursuit (RSAMP), is presented to prune the redundant terms of memory polynomial based models for PA behavioral modeling. Unlike other CS based model pruning techniques, RSAMP method can estimate the sparsity level of the models adaptively with a regularized stagewise backtracking process. Using this method, the dominant sparse terms can be efficiently estimated based on the chosen supports without requiring the sparity level as an input parameter. Experiment results show that the RSAMP algorithm can efficiently construct a sparse behavioral model with very few terms, but almost have the same model performance with the full model.

Sparsity Adaptive Estimation of Memory Polynomial Based Models for Power Amplifier Behavioral Modeling

In this paper, we propose a new sparse framework for the design of the behavioral model and digital predistorter of a broadband power amplifier (PA). We start by formulating the Volterra kernel to multidimensional memory polynomial by considering the high-order dynamic truncation of the Volterra model. Then we show how an estimate of the most significant coefficients may be obtained using a matching pursuit (MPT) algorithm by exploiting the sparsity of the model. After the indices of the nonzero coefficients are roughly estimated, the block exact Householder inverse QR-decomposition-based recursive least squares (HIQRD-RLS) algorithm is utilized to estimate the sparse model complex coefficients. For broadband nonlinear PAs, the proposed approach is demonstrated to achieve the best performance among the well-known traditional approaches in terms of in-band and out-of-band specifications. The proposed approach is also validated by evaluating the digital predistortion (DPD) performance on a Class-AB PA in terms of adjacent channel power ratio (ACPR). © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Qing Dong

Papers

How does partitioning matter for 3D floorplanning

Structured analog circuit design and MOS transistor decomposition for high accuracy applications

Structured Placement with Topological Regularity Evaluation

Sparsity Adaptive Estimation of Memory Polynomial Based Models for Power Amplifier Behavioral Modeling

A new sparse design framework for broadband power amplifier behavioral modeling and digital predistortion