Q
Quming Zhou
Researcher at Rice University
Publications - 14
Citations - 755
Quming Zhou is an academic researcher from Rice University. The author has contributed to research in topics: Combinational logic & Logic gate. The author has an hindex of 9, co-authored 14 publications receiving 732 citations. Previous affiliations of Quming Zhou include Baker Hughes.
Papers
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Journal ArticleDOI
Gate sizing to radiation harden combinational logic
Quming Zhou,Kartik Mohanram +1 more
TL;DR: A gate-level radiation hardening technique for cost-effective reduction of the soft error failure rate in combinational logic circuits is described, which uses a novel gate (transistor) sizing technique that is both efficient and accurate.
Proceedings ArticleDOI
Transistor sizing for radiation hardening
Quming Zhou,Kartik Mohanram +1 more
TL;DR: In this article, an efficient and accurate numerical analysis technique to simulate single event upsets (SEUs) in logic circuits is presented, which can be easily integrated into design automation tools to harden sensitive portions of logic circuits.
Proceedings ArticleDOI
Cost-effective radiation hardening technique for combinational logic
Quming Zhou,Kartik Mohanram +1 more
TL;DR: The technique, which decouples the physical from the logical aspects of soft error susceptibility of a gate, uses a gate (transistor) sizing technique that is both efficient and accurate (in comparison to SPICE).
Proceedings ArticleDOI
Parallel domain decomposition for simulation of large-scale power grids
TL;DR: Results for circuits with more than four million nodes indicate that parallel DD with LU factorization is most suitable for power grid simulation, but for densely connected power grids, parallelDD with additive Schwarz preconditioning offers maximum scalability and best performance.
Proceedings ArticleDOI
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
TL;DR: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described and a simple, highly accurate model for the SEU robustness of a logic gate is developed.