This paper discusses the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.

Design for Testability&#8212;A Survey

Design for testability&#8212;A survey

Experiences in Fault Tolerant Computing, 1947-1971.- Evolution of Fault Tolerant Switching Systems in AT&T.- Fault Tolerance in Tandem Computer Systems.- Evolution of Reliable Computing in Hitachi and Autonomous Decentralized System.- A History of Research in Fault Tolerant Computing at SRI International.- The Evolution of Fault Tolerant Computing at the Charles Stark Draper Laboratory, 1955-85.- The Evolution of Fault Tolerant Computing at the Jet Propulsion Laboratory and at UCLA: 1955-1986.- Dependable Computing and Fault Tolerance at LAAS: a Summary.- Reliable Digital Systems and Related Stanford University Research.- Design Fault Tolerance.- The Evolution of Fault Tolerant Computing at the University of Illinois.- The Evolution of Fault Tolerant Computing at the University of Michigan.- Experimental Research in Reliable Computing at Carnegie Mellon University.- A History of Research in Fault Tolerant Computing at the Grenoble University.- Research Activities on FTC in Japan.- The Evolution of Dependable Computing in Italy.- Fault Tolerant Computing Systems in Germany.- The Technical Committee on Fault Tolerant Computing of The IEEE Computer Society.- Biographies.- Author Index.

The evolution of fault-tolerant computing

A probabilistic treatment of general combinational networks has been developed. Using the notions of the probability of a signal and signal independence, algorithms have been presented to calculate the probability of the output of a logic circuit being 1. Simplifications to the algorithm result when sets of input probabilities are given the same value, and this process called bundling is described in the paper. Finally, a series of examples illustrate the application of the probabilistic approach to the analysis of faulty logic circuits.

Analysis of Logic Circuits with Faults Using Input Signal Probabilities

Triple-modular redundancy (TMR) is a classical technique for improving the reliability of digital systems. However, applying TMR to microcomputer systems may not improve overall system reliability because voter circuits may contribute as much to system unreliability as the microprocessors themselves. We examine the issues that affect the effectiveness of TMR for transient recovery and the reliability of semiconductor memory systems. With careful application, TMR can improve the mission time of a small system by a factor of 3 or more.

Microcomputer reliability improvement using triple-modular redundancy

The paper discusses two methods to evaluate the signal reliability of the output of logical circuits. It is known that faults present in a circuit will not always cause the output of the circuit to be incorrect. Given the probability of faults occurring in the circuit and the probabilities of the input combinations, it is possible to determine the likelihood of the output being correct. The signal reliability of the output is thus defined as the probability that the circuit output is correct. The first method evaluates the contribution of each fault to the reliability of the circuit and requires the enumeration of the behavior of each fault in the entire fault set. The use of McCluskey and Clegg's characterization of faulty networks by evaluating the functional equivalence classes of the network is a way to reduce the amount of computation involved. Lower bounds can be obtained by considering a restricted fault set, for example, the single fault set. The second method uses a probabilistic model of logical circuits and consists of straightforward operations which can easily be automated. The method also yields the signal reliability and has the capability of very easily specifying the individual fault probabilities of all the circuit lines independently.

The Probability of a Correct Output from a Combinational Circuit

The technique of hybrid redundancy has been used to protect those portions of a digital system which have to be made ultrareliable. Siewiorek and McCluskey have presented a new switch design for hybrid redundancy which is shown to be of less complexity than other switch designs presented in the literature.

R.C. Ogus

Papers

The Probability of a Correct Output from a Combinational Circuit

Fault-Tolerance of the Iterative Cell Array Switch for Hybrid Redundancy