A phase and frequency detector IC is presented that operates up to an NRZ bit rate of 8 Gb/s. The IC comprises a phase detector (PD), a quadrature phase detector (QPD), and frequency detector (FD). In the PD and QPD the VCO signal and the quadrature VCO signal are sampled by the NRZ input signal. The two beat notes provided by this operation are subsequently processed in the FD. The superposition of the FD output and the PD output signals are then fed into a passive loop filter (lag/lead filter). The loop filter and the VCO are external components. The measured pull-in range is >+or-100 MHz at 8 Gb/s. The measured r.m.s. time jitter of the extracted clock is less than 1.9 ps for a pseudorandom bit sequence (PRBS) length of 2/sup 23/-1. A 0.9- mu m 12-GHz f/sub T/ silicon bipolar process was used to fabricate the chip with a total power consumption of 1.4 W. >

A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s

In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent “size” of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block. Consequently, an increasingly larger equivalent capacitor may be implemented by adding additional digital stages, each of which requires a small incremental integrated circuit area. The power dissipation of the digital integration block is reduced by incorporating a decimation stage to reduce the required operating frequency of the remainder of the digital integration block.

Digitally-synthesized loop filter circuit particularly useful for a phase locked loop

Two important questions in high-speed networking are firstly, how to provide Gbit/s networking at low cost and secondly, how to provide a flexible low-level network interface so that applications can control their data from the instant it arrives.We describe some work that addresses both of these questions. The Jetstream Gbit/s LAN is an experimental, low-cost network interface that provides the services required by delay-sensitive traffic as well as meeting the performance needs of current applications. Jetstream is a combination of traditional shared-medium LAN technology and more recent ATM cell- and switch-based technology.Jetstream frames contain a channel identifier so that the network driver can immediately associate an incoming frame with its application. We have developed such a driver that enables applications to control how their data should be managed without the need to first move the data into the application's address space. Consequently, applications can elect to read just a part of a frame and then instruct the driver to move the remainder directly to its destination. Individual channels can elect to receive frames that have failed their CRC, while applications can specify frame-drop policies on a per-channel basis.Measured results show that both kernel- and user-space protocols can achieve very good throughput: applications using both TCP and our own reliable byte-stream protocol have demonstrated throughputs in excess of 200 Mbit/s. The benefits of running protocols in user-space are well known- the drawback has often been a severe penalty in the performance achieved. In this paper we show that it is possible to have the best of both worlds.

/pdf/user-space-protocols-deliver-high-performance-to-1i8j1wvh1a.pdf

User-space protocols deliver high performance to applications on a low-cost Gb/s LAN

In the future LHC experiments, some data acquisition and trigger links will be based on Gbit/s optical fiber networks. In this paper, a configurable radiation tolerant Gbit/s serializer (GOL) is presented that addresses the high-energy physics experiments requirements. The device can operate in four different modes that are a combination of two transmission protocols and two data rates (0.8 Gbit/s and 1.6 Gbit/s). The ASIC may be used as the transmitter in optical links that, otherwise, use only commercial components. The data encoding schemes supported are the CIMT (G-Link) and the 8B/10B (Gbit-Ethernet & Fiber Channel). To guarantee robustness against total dose irradiation effects over the lifetime of the experiments, the IC was fabricated in a standard 0.25 μm CMOS technology employing radiation tolerant layout practices.

/pdf/a-radiation-tolerant-gigabit-serializer-for-lhc-data-5ce0x3exrs.pdf

A radiation tolerant gigabit serializer for LHC data transmission

The design and performance of two essential analog circuits in optical-fiber receivers is described. A time-interleaved decision circuit is capable of regenerating 35-mV nonreturn-to-zero (NRZ) data inputs to full logic levels at 1.1 Gb/s with 10/sup -11/ bit error rate (BER), and a phase-locked loop (PLL) extracts the clock from a 2/sup 23/ long pseudorandom sequence at 1.5 Gb/s with 13-ps r.m.s. jitter. The two circuits have been implemented as 1- mu m NMOS ICs, and in their core area dissipate 200 and 350 mW, respectively. >

NMOS IC's for clock and data regeneration in gigabit-per-second optical-fiber receivers

The authors designed a set of four ICs to provide encoding, multiplexing, clock extraction/demultiplexing, and decoding for gigabit-rate serial data transmission. These chips form a high bandwidth data link for point-to-point communication. A new line code is implemented that provides DC balance, efficient encoding, framing, and simple clock extraction. Embedded in the code is a fixed transition used by the phase/frequency locked loop (PLL) for simple clock extraction and frame synchronization. Unlike other links, this PLL requires no trimming for data retiming, either in production or later. An on-chip voltage-controlled oscillator (VCO) with a tuning range of 1.1-1.6 GHz is available for use with the PLL. With this chip set the authors demonstrated a transmission rate of 16 bits in parallel at 75 MHz or, with encoding overhead, a serial rate of 1.5 Gb/s. >

A 1.5 Gb/s link interface chipset for computer data transmission

A gigabit-rate data link consisting of four custom silicon bipolar chips for transmitting parallel data between elements of a distributed computer system is discussed. A transmission rate of 16 bits in parallel at 50 MHz or with encoding overhead, a serial rate of 1 Gb/s is demonstrated. The link utilizes an encoding scheme that is bandwidth efficient. Unlike other links, the phase/frequency-locked loop also provides frame synchronization and requires no trimming for data retiming, either in production or later. >

R.C. Walker

Papers

A 1.5 Gb/s link interface chipset for computer data transmission

A chipset for gigabit rate data communication (using optical fibres)