Journal ArticleDOI
A 1.5 Gb/s link interface chipset for computer data transmission
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TLDR
A set of four ICs to provide encoding, multiplexed, clock extraction/demultiplexing, and decoding for gigabit-rate serial data transmission for point-to-point communication is designed.Abstract:
The authors designed a set of four ICs to provide encoding, multiplexing, clock extraction/demultiplexing, and decoding for gigabit-rate serial data transmission. These chips form a high bandwidth data link for point-to-point communication. A new line code is implemented that provides DC balance, efficient encoding, framing, and simple clock extraction. Embedded in the code is a fixed transition used by the phase/frequency locked loop (PLL) for simple clock extraction and frame synchronization. Unlike other links, this PLL requires no trimming for data retiming, either in production or later. An on-chip voltage-controlled oscillator (VCO) with a tuning range of 1.1-1.6 GHz is available for use with the PLL. With this chip set the authors demonstrated a transmission rate of 16 bits in parallel at 75 MHz or, with encoding overhead, a serial rate of 1.5 Gb/s. >read more
Citations
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Journal ArticleDOI
A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s
TL;DR: In this article, a phase and frequency detector IC is presented that operates up to an NRZ bit rate of 8 Gb/s, which includes a phase detector, a quadrature phase detector (QPD), and a frequency detector (FD).
Patent
Digitally-synthesized loop filter circuit particularly useful for a phase locked loop
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Proceedings ArticleDOI
User-space protocols deliver high performance to applications on a low-cost Gb/s LAN
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Journal ArticleDOI
NMOS IC's for clock and data regeneration in gigabit-per-second optical-fiber receivers
S.K. Enam,Asad A. Abidi +1 more
TL;DR: In this article, the design and performance of two essential analog circuits in optical fiber receivers is described, which are implemented as 1- mu m NMOS ICs, and in their core area dissipate 200 and 350 mW, respectively.
Journal ArticleDOI
A two-chip 1.5-GBd serial link interface
Richard C. Walker,Cheryl Stout,Jieh-Tsorng Wu,Benny W. H. Lai,C.-S. Yen,Thomas Hornak,Patrick Petruno +6 more
TL;DR: The line code and handshake protocol have been accepted by the serial-HIPPI implementor's group for serially transmitting 800-Mb/s HIPPI data, an ANSI standard, and by SCI-FI, an IEEE standard for interconnecting cooperating computers.
References
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Patent
Phase locked loop for clock extraction in gigabit rate data communication links
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Journal ArticleDOI
Gigahertz voltage-controlled ring oscillator
K.E. Syed,A.A. Abidi +1 more
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Proceedings ArticleDOI
A chipset for gigabit rate data communication (using optical fibres)
TL;DR: A gigabit-rate data link consisting of four custom silicon bipolar chips for transmitting parallel data between elements of a distributed computer system is discussed and the phase/frequency-locked loop also provides frame synchronization and requires no trimming for data retiming, either in production or later.