R
R. H. Seacat
Researcher at University of Arizona
Publications - 6
Citations - 162
R. H. Seacat is an academic researcher from University of Arizona. The author has contributed to research in topics: Scintillation & Simulated annealing. The author has an hindex of 4, co-authored 6 publications receiving 161 citations.
Papers
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Journal Article
A full-field modular gamma camera.
Tom D. Milster,J. N. Aarsvold,Harrison H. Barrett,A. L. Landesman,L. S. Mar,Dennis D. Patton,T. J. Roney,Robert K. Rowe,R. H. Seacat +8 more
TL;DR: A modular gamma ray camera is described that gives useful image information over its entire crystal face, made possible by a unique application of digital electronics and optimal position estimation using maximum likelihood estimates.
Journal ArticleDOI
Digital Position Estimation for the Modular Scintillation Camera
TL;DR: In this article, two Bayesian estimators, namely maximum-likelihood (ML) and minimum-meansquare-error (MS), were used to estimate the position of the PMT signal.
Proceedings ArticleDOI
Modular Scintillation Cameras: A Progress Report
J. N. Aarsvold,Harrison H. Barrett,J.C. | Chen,A. L. Landesman,Tom D. Milster,Dennis D. Patton,T. J. Roney,Robert K. Rowe,R. H. Seacat,L. M. Strimbu +9 more
TL;DR: Modular scintillation cameras are gamma cameras with relatively small crystal faces, a small number of photomultiplier tubes (PMTs), and independent processing electronics and logarithmic matched filtering and likelihood windowing are introduced, two processing techniques that result from exploitations of the Poisson model of the distribution of photopeak events.
Proceedings ArticleDOI
TRIMM: A High Speed Parallel Processor For Optimization And Estimation Problems
TL;DR: The design of a parallel processor containing 60 32-bit processors with on-chip floating point hardware, 60 Mbytes of memory, hardware random number generation, and a high bandwidth, re-configurable interprocessor communications system is discussed.
Book ChapterDOI
TRIMM: A Parallel Processor for Image Reconstruction by Simulated Annealing
TL;DR: A parallel processor using 60 transputers plus a global processor with broad-cast addressing and hardware random number generation with initial performance tests demonstrate a calculation speed for image reconstruction greater than that of a Convex C240.