A modular, adaptive power management system includes a hard disk drive controller, a read channel module, a host interface controller and a power manager system. The hard disk controller includes a processor executing firmware, and the host interface controller provides for host access via a host interface. The system includes a power island register and an oscillation control register. Both registers are writable via the firmware and via the host interface. The hard disk controller, the interface controller, the read channel module and the power manager system are implemented across two or more distinct power islands and use two or more distinct clocks. Power to the two or more distinct power islands is at least in part controlled by the power manager system via the power island register, and the two or more distinct clocks are each controlled by the power manager system via the oscillation control register.

Systems and methods for modular power management

Embodiments include collecting, from each of a plurality of controllers of a node having a plurality of components, component power consumption. Each of the plurality of controllers is associated with one or more of the components. The component power consumptions are provided to the controllers. A node power consumption for the node is determined based, at least in part, on the component power consumption. The power cap is determined for the plurality of components. A power differential power is determined as a difference between the node power consumption and the power cap for the plurality of components. A proportion of the node power consumption consumed by the component is determined based on the component power consumption of the component. A local power budget is computed for the component based, at least in part, on the power differential and the proportion of the node power consumption consumed by the component.

Distributed power budgeting

Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.

Hardware synthesis using thermally aware scheduling and binding

Disclosed is an integrated circuit (200) comprising a plurality of cores (110, 110), at least some of the cores being located in different power domains (VDD1, VDD2), each core being surrounded by a test wrapper (220) comprising a plurality of wrapper cells (128, 230), wherein each of said test wrappers are located in a single power domain (VDD3) and each plurality of wrapper cells comprises wrapper output cells (230) each arranged to output a signal from its associated core, each of said wrapper output cells comprising an output level shifter (232, 240) for shifting the voltage of said signal to the voltage of the single power domain (VDD3). A method for testing such an IC and standard library cells for designing such an IC are also disclosed.

Testable integrated circuit and test method therefor

One or more portions of the design (e.g., components, channels, or portions thereof) can be assigned instances of one or more component power domains (CPDs). Assigning an instance of a CPD to a design element (or to a portion thereof) can indicate, for example, whether the element can be switched on and off, or whether the element can operate over a range of voltages. The CPD instances can, in turn, be assigned to one or more design power domains (DPDs). Assignments of a CPD to a DPD can be evaluated according to a set of compatibility rules. Two or more electronic design elements can be connected by one or more signal paths. Organizing the CPD instances into DPDs can aid in finding signal paths that cross from a first DPD to a second DPD. To improve the reliability of signal paths traversing a DPD boundary, one or more power domain interface (PDI) components can be created to handle the signal paths at the boundary.

Automating power domains in electronic design automation

The present invention relates to real-time adaptive control for best Integrated Circuit (IC) performance. The adaptive behavior is carried out on a local basis. The system is partitioned into different islands (30). Each island (30) is controlled and its working conditions are modified depending on some parameters. The remainder of the chip is controlled as well, depending on other parameters. This requires that each island (30) has a local controller (36) communicating with a global controller (42). The main control parameters are e.g. supply voltage, threshold voltage and clock frequency.

Real-time adaptive control for best ic performance

Travel Report to the 2005 IEEE International Symposium on Circuits and Systems © Koninklijke Philips Electronics N.V. 2005 iii PR-TN 2005/01087 Unclassified iv © Koninklijke Philips Electronics N.V. 2005 Unclassified PR-TN 2005/01087

2005 IEEE International Symposium on Circuits and Systems

An IC (10) is disclosed that comprises a first power supply rail (110) and a second power supply rail (130) and a plurality of circuit portions (100, 400, 700) respectively coupled between the first power supply rail (110) and the second power supply rail (130). A first circuit portion thereof is coupled to the first power supply rail (110) via a first conductive path comprising a first enable switch (120), and to a test mode power supply rail (110, 310) via a second conductive path for enabling a quiescent current measurement (610) of the first circuit portion in a test mode of the integrated circuit (10). The second conductive path comprises a sensing switch (220) for coupling the first portion to the test mode power supply rail (110, 310) in the test mode. The test mode power supply rail may be same rail as the first power supply rail (110), in which case the IC (10) may comprise a current sensor (230) to facilitate on-chip IDDQ measurements. The IC (10) of the present invention allows for accurate IDDQ measurements of parts of the IC at little area overhead cost only.

Integrated circuit with iddq test facilities and ic iddq test method

A 32-bit ALU has been implemented in the baseline Philips-Motorola-ST 0.10um triple-VT CMOS technology. The ALU core has been designed with a combined dynamic/static design approach aiming at high-speed operation and standard cells based design. It runs at frequencies ranging from 3.8 GHz to 5.4 GHz (with nominal supply at room temperature) depending on the actual fabrication process corner.

R. I. M. P. Meijer

Papers

Real-time adaptive control for best ic performance

2005 IEEE International Symposium on Circuits and Systems

Integrated circuit with iddq test facilities and ic iddq test method

A 260ps Quasi-static ALU in 90nm CMOS