Layout optimization involves interconnection wiring modifications, which improve aesthetic appearance, fabrication characteristics, routability, and reliability of routed boards/chips. Requirements and capabilities of a general purpose layout optimizer are presented, then organization and processing flow of the program are outlined. The functional decomposition and modular structure of this system are presented. Results achieved by using the verifier/optimizer on large printed circuit boards and gate arrays are given.

Verification and optimization for LSI & PCB layout

Verification and Optimization for LSI a PCB Layout

Experiments to compare the performance of several widely-used interconnection routing algorithms are described. Examples of the experimental results are given and their implications discussed.

https://ieeexplore.ieee.org/iel4/5781/15428/00748946.pdf

Analytical And Experimental Analysis Of Routing Algorithms

Automatic routing programs produce layouts which contain features that could be improved. This paper describes straightforward techniques for layout improvement that are routing algorithm independent.

Automatic PC board routing cleanup procedures

We have recently developed an algorithm for the generation of Steiner trees in a barrier-free environment The algorithm and related mathematical material appear elsewhere (1); the purpose of this note is to informally describe the concepts underlying our approach, and to demonstrate the computational feasibility of the method Our problem model consists of a two-dimensional rectilinear grid containing nodes which must be connected by orthogonal line segments The objective is to connect the set of nodes with a collection of lines having minimum total length As will be demonstrated, our technique may be manually applied to problems of 25-50 points; much larger problems could be solved by utilizing computer processing While the algorithm has not yet been proven to produce minimum length trees, we maintain that typical results are at least very nearly minimal We hope to stimulate critical reactions to the following material by presenting it informally in this Newsletter

R. J. Smith

Papers

Automatic PC board routing cleanup procedures

Generation of Steiner tree connections in a barrier-free environment