Layout optimization involves interconnection wiring modifications, which improve aesthetic appearance, fabrication characteristics, routability, and reliability of routed boards/chips. Requirements and capabilities of a general purpose layout optimizer are presented, then organization and processing flow of the program are outlined. The functional decomposition and modular structure of this system are presented. Results achieved by using the verifier/optimizer on large printed circuit boards and gate arrays are given.

Verification and optimization for LSI & PCB layout

Verification and Optimization for LSI a PCB Layout

Automatic routing programs produce layouts which contain features that could be improved. This paper describes straightforward techniques for layout improvement that are routing algorithm independent.

W. J. Kaminsky

Papers

Automatic PC board routing cleanup procedures