While many algorithm-based fault tolerance (ABFT) schemes have been proposed to detect soft errors offline in the fast Fourier transform (FFT) after computation finishes, none of the existing ABFT schemes detect soft errors online before the computation finishes. This paper presents an online ABFT scheme for FFT so that soft errors can be detected online and the corrupted computation can be terminated in a much more timely manner. We also extend our scheme to tolerate both arithmetic errors and memory errors, develop strategies to reduce its fault tolerance overhead and improve its numerical stability and fault coverage, and finally incorporate it into the widely used FFTW library - one of the today's fastest FFT software implementations. Experimental results demonstrate that: (1) the proposed online ABFT scheme introduces much lower overhead than the existing offline ABFT schemes; (2) it detects errors in a much more timely manner; and (3) it also has higher numerical stability and better fault coverage.

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Correcting soft errors online in fast fourier transform

1 Introduction 12 Faults in Nanoscale Circuits 32.1 Error Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.1.1 Permanent Errors . . . . . . . . . . . . . . . . . . . . . . 32.1.2 Intermittent Errors . . . . . . . . . . . . . . . . . . . . . 32.1.3 Transient Errors . . . . . . . . . . . . . . . . . . . . . . . 42.2 Error Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2.1 Manufacture Process . . . . . . . . . . . . . . . . . . . . 42.2.2 Physical Changes During Operation . . . . . . . . . . . . 52.2.3 Internal Noise . . . . . . . . . . . . . . . . . . . . . . . . 62.2.4 External Noise . . . . . . . . . . . . . . . . . . . . . . . 72.3 Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Static Fault Tolerance 93.1 Hardware Redundancy . . . . . . . . . . . . . . . . . . . . . . . 93.1.1 Voters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.2 Time Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . 123.3 Information Redundancy . . . . . . . . . . . . . . . . . . . . . . 133.4 Hybrid Approaches . . . . . . . . . . . . . . . . . . . . . . . . . 154 Dynamic Fault Tolerance 174.1 Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.1.1 Checkers . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2 Fault Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.3 Fault Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.4 Reconﬁgurable Arrays . . . . . . . . . . . . . . . . . . . . . . . 235 Conclusions 24

On Fault Tolerance Techniques towards Nanoscale Circuits and Systems

A novel feature-domain two-dimensional (2-D) motion estimation system based on the straight-line Hough transform (SLHT) is presented. This system implements the motion estimation technique proposed in an earlier work that represents objects uniquely by straight-line approximations of the boundary {(/spl theta/, p)} and estimates the motion parameters from shifts in the /spl theta/-p space. It operates on 256/spl times/256 pixel binary images and consists of two main blocks. The first block does preprocessing work including smoothening the boundary, tracing and integrating the contours, and detecting dominant points. The second block computes the Hough transform on contour segments as well as the rotation and translation parameters. Each of the modules has been implemented (gate level) and simulated using Mentor Graphics tools. Finally, the experimental results have been presented and compared with the results of the software implementation.

Hardware design of a 2-D motion estimation system based on the Hough transform

In recent years, there have been several proposals for the realization of models inspired to biological solutions for pattern recognition. In this work we propose a new approach, based on a hierarchical modular structure, to realize a system capable to learn by examples and recognize objects in digital images. The adopted techniques are based on multiresolution image analysis and neural networks. Performance on two different data sets and experimental timings on a single instruction multiple data (SIMD) machine are also reported.

/pdf/neural-recognition-in-a-pyramidal-structure-20068f511v.pdf

Neural recognition in a pyramidal structure

Iterative division algorithms based on multiplication are popular because they are fast and may utilize an already existing hardware multiplier. Two popular methods based on multiplication are Newton-Raphson and Goldschmidt's algorithm. To achieve concurrent error correction, Time Shared Triple Modular Redundancy (TSTMR) may be applied to both kinds of dividers. The hardware multiplier is divided into thirds, and the rest of the divider logic replicated around each part, to provide three independent dividers. While this reduces the size of the fault-tolerant dividers over that of traditional TMR, latency may be increased. However, both division algorithms can be modified to use lower precision multiplications during the early iterations. This saves multiply cycles and, hence, produces a faster divider.

Fault-tolerant Newton-Raphson and Goldschmidt dividers using time shared TMR

In 1983 an Italian research program was begun for the design, simulation and construction of a multiprocessor image processing system. After a first phase devoted to the comparison of suggested and existing systems and to the definition of a set of benchmarks, a new system was defined. The structure of this new system is introduced here: it is based on a fine-grained pyramid of processors built up by means of a pyramidal cell implemented on a VLSI multiprocessor chip. The peculiarities and the capabilities of the processing element are highlighted. The complete hardware and software system has been fully designed and is described. A first working prototype has been built and is now operational.

The PAPIA system

Time redundancy is suggested as a viable solution for the two-dimensional fast Fourier transform (FFT) array directly corresponding to the FFT flow graph. Two approaches are presented, one based on interstage reconfiguration and the other on intrastage reconfiguration, both allowing for survival to multiple faults with limited increase of network complexity and very small hard-core sections. With both approaches, the processing speed in the presence of faults is halved with respect to the nominal speed. Reliability and survival ratios to multiple faults are evaluated for the two cases, taking into account the area increments necessary for fault tolerance. >

Fault-tolerance in FFT arrays: time-redundancy approaches

This paper describes a chip-set for the Generalized Hough Transform suitable for a modular set-up of an object recognition subsystem.The target application is the real-time localization of bidimensional objects of arbitrary shape that cannot be described analytically. A functional description of each module of the chipset is given; the architectural aspects of the project are analyzed, together with the results of the prototyping phase, which addresses the problem of VLSI integration.

A Chip-set For The Hough Transform

Fault tolerance in VLSI/WSI FFT arrays acquires relevance when defects and run-time faults become significant, due to large dimensions of processors and arrays. Then, both restructuring to overcome end-of-production defects and reconfiguration to overcome run-time faults are required, to achieve the dual purposes of higher yield and higher reliability.

Adopting as basic FFT network the two-dimensions array that directly corresponds to the FFT flow graph, the usual structure redundancy techniques tailored for two-dimensions arrays reconfiguration are not well applicable, since the limited locality of this network leads to relevant area increase due to the augmented interconnection structure.

In this paper,time redundancy is suggested as a viable alternative for the two-dimensions FFT array; two different solutions are presented, one based oninter-stage reconfiguration, the other one adoptingintra-state reconfiguration, both allowing for survival to multiple faults with limited increase of network complexity and very small hard-core sections. As usual in many time redundancy methods, both approaches result in a processing speed equal to half the processing speed granted by an ideal, fault-free device.

Reliability and survival ratios to multiple faults are evaluated for the two cases, taking into account also the area increments necessary for fault tolerance. The reliability evaluations allow for a direct comparison of the two solutions.

R. Negrini

Papers

The PAPIA system

Fault-tolerance in FFT arrays: time-redundancy approaches

A Chip-set For The Hough Transform

Fault tolerance in FFT arrays: time redundancy approaches

An approach to fault-tolerance in architectures for discrete Fourier transforms