At-speed test has become a requirement in IC tech- nologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special chal- lenges to the successful application of structural at- speed tests. In this paper we characterize these prob- lems on commercial ASICs in order to understand how to implement more effective solutions. consumption. Depending on such parameters as gate count, DFT strategies, package type, and other fac- tors, the impact of this problem can range from non- existent to severe. In this paper, we discuss the prac- tical issues associated with power consumption during at-speed tests. We begin by delineating in more detail the nature of power-related phenomena encountered in structured speed tests. We talk about various de- sign features that can be applied to somewhat miti- gate test mode power dissipation. In Section 2, we give a more precise definition of the IR-drop problem which is the focus of this pa- per. We compare IR-drop in slow speed and at-speed structural tests, and also compare it with functional IR-drop. We narrow the focus further to the topic of toggle activity or "switching density" during struc- tured at-speed tests. In Section 3.4 we describe the notion of "quiet" patterns and how they are gener- ated. We follow up with a report of the results we have obtained in experimentation on industrial ASIC designs. Finally we give our suggestions for future work in this area and conclude the paper.

A case study of ir-drop in structured at-speed testing

Single scan chain architectures suffer from long test application time, while multiple scan chain architectures require large pin overhead and are not supported by boundary scan. We present a novel method to allow a single input line to support multiple scan chains. By appropriately connecting the inputs of all circuits under test during ATPG process such that the generated test patterns can be broadcast to all scan chains when actual testing is executed, we show that 177 and 280 test patterns are enough to detect all detectable faults in all 10 ISCAS'85 combinational circuits and 10 largest ISCAS'89 sequential circuits, respectively.

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Using a single input to support multiple scan chains

The McKinley processor is the result of a joint design effort between Intel and Hewlett-Packard engineers, and is the second processor implementation of the Itanium/sup TM/ processor family (IPF) architecture. This paper describes the methodology developed for testing a complex high-performance microprocessor design. An overview of the processor is presented, along with the goals for the test methodology. Details of the test control blocks, scan methodology, and clocking are given. The scanlatch design, trade-offs and verification processes are discussed, along with some details of ATPG modeling and memory array testing. Finally, some results are presented.

Debug methodology for the McKinley processor

1. Built-In Self-Test. Introduction. Design for Testability. Generation of Test Vectors. Compaction of Test Responses. BIST Schemes for Random Logic. BIST for Memory Arrays. 2. Generation of Test Vectors. Additive Generators of Exhaustive Patterns. Other Generation Schemes. Two-Dimensional Generators. 3. Test-Response Compaction. Binary Adders. 1's Complement Adders. Rotate-Carry Adders. Cascaded Compaction Scheme. 4. Fault Diagnosis. Analytical Model. Experimental Validation. The Quality of Diagnostic Resolution. Fault Diagnosis in Scan-Based Designs. 5. BIST of Data-Path Kernel. Testing of ALU. Testing of the MAC Unit. Testing of the Microcontroller. 6. Fault Grading. Fault Simulation Framework. Functional Fault Simulation. Experimental Results. 7. High-Level Synthesis. Implementation-Dependent Fault Grading. Synthesis Steps. Simulation Results. 8. ABIST at Work. Testing of Random Logic. Memory Testing. Digital Integrators. Leaking Integrators. 9. Epilog. Bibliography. A. Tables of Generators. B. Assembly Language. Index.

Arithmetic Built-In Self-Test for Embedded Systems

We present a technique for making a circuit ready for logic built-in self test by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

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X-masking during logic BIST and its impact on defect coverage

This study provides bridging fault simulation data obtained from the AMD-K6 microprocessor. It shows that: (1) high stuck-at fault coverage (99.5%) implies high bridging fault coverage; (2) coverage of a bridging fault by both wired-AND and wired-OR behavior does not guarantee detection of that fault when compared against a more accurate (transistor-level simulation) modeling method. A set of netname pairs representing bridging fault sites were extracted from layout and used for each fault modeling method. Results show that pattern generation should be driven by the most accurate modeling method when pursuing 100% bridging coverage, since less accurate methods will not necessarily converge to a high quality result.

A comparison of bridging fault simulation methods

This paper describes the testability features and test pattern development methodologies for the AMD-K6/sup TM/ microprocessor. The embedded design for testability (DFT) structures and test strategy provide high quality manufacturing tests.

R.S. Fetherston

Papers

A comparison of bridging fault simulation methods

Testability features of AMD-K6/sup TM/ microprocessor